On Tue, Aug 14, 2018 at 3:11 PM James Zhu <jzhums at gmail.com> wrote:
>
> From: Feifei Xu <Feifei.Xu at amd.com>
>
> With PSP firmware loading, TMR mc address is supposed to be used.
>
> Signed-off-by: James Zhu <James.Zhu at amd.com>
Series is:
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c | 13 +++++++++----
> 1 file changed, 9 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
> index 3966f1b..fc9db7b 100644
> --- a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
> @@ -656,9 +656,14 @@ static void uvd_v7_0_mc_resume(struct amdgpu_device *adev)
> for (i = 0; i < adev->uvd.num_uvd_inst; ++i) {
> if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
> WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
> - lower_32_bits(adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].mc_addr));
> + i == 0 ?
> + adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].tmr_mc_addr_lo:
> + adev->firmware.ucode[AMDGPU_UCODE_ID_UVD1].tmr_mc_addr_lo);
> WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
> - upper_32_bits(adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].mc_addr));
> + i == 0 ?
> + adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].tmr_mc_addr_hi:
> + adev->firmware.ucode[AMDGPU_UCODE_ID_UVD1].tmr_mc_addr_hi);
> + WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_OFFSET0, 0);
> offset = 0;
> } else {
> WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
> @@ -666,10 +671,10 @@ static void uvd_v7_0_mc_resume(struct amdgpu_device *adev)
> WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
> upper_32_bits(adev->uvd.inst[i].gpu_addr));
> offset = size;
> + WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_OFFSET0,
> + AMDGPU_UVD_FIRMWARE_OFFSET >> 3);
> }
>
> - WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_OFFSET0,
> - AMDGPU_UVD_FIRMWARE_OFFSET >> 3);
> WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_SIZE0, size);
>
> WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW,
> --
> 2.7.4
>
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