PSP engine only allocate space for firmware.
mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW/HIGH is for firmware TMR address.
The other two address are for HEAP/Session.
Regards!
James Zhu
On 2018-08-13 12:16 AM, Quan, Evan wrote:
>
> Why only the mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW/HIGH use the new
> tmr_mc_addr? And the mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW/HIGH and
> mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW/HIGH still use the old
> adev->vcn.gpu_addr?
>
>
> Regards,
>
> Evan
>
> ------------------------------------------------------------------------
> *From:* amd-gfx <amd-gfx-bounces at lists.freedesktop.org> on behalf of
> James Zhu <jzhums at gmail.com>
> *Sent:* Friday, August 10, 2018 12:31:42 AM
> *To:* amd-gfx at lists.freedesktop.org
> *Cc:* Deucher, Alexander; Gao, Likun; Zhu, James; Huang, Ray
> *Subject:* [PATCH v2 5/5] drm/amdgpu:add VCN booting with firmware
> loaded by PSP
> From: Likun Gao <Likun.Gao at amd.com>
>
> Setup psp firmware loading for VCN, and make VCN block
> booting from tmr mac address.
>
> Signed-off-by: James Zhu <James.Zhu at amd.com>
> Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
> ---
> Â drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 17 +++++++++------
>  drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c  | 38
> ++++++++++++++++++++++++++-------
> Â 2 files changed, 40 insertions(+), 15 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
> index 878f62c..77c192a 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
> @@ -111,9 +111,10 @@ int amdgpu_vcn_sw_init(struct amdgpu_device *adev)
> Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â version_major, version_minor, family_id);
> Â Â Â Â Â Â Â Â }
>
> -Â Â Â Â Â Â bo_size =
> AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8)
> -Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â +Â AMDGPU_VCN_STACK_SIZE + AMDGPU_VCN_HEAP_SIZE
> +Â Â Â Â Â Â bo_size = AMDGPU_VCN_STACK_SIZE + AMDGPU_VCN_HEAP_SIZE
> Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â +Â AMDGPU_VCN_SESSION_SIZE * 40;
> +Â Â Â Â Â Â if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
> +Â Â Â Â Â Â Â Â Â Â Â Â Â Â bo_size +=
> AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8);
> Â Â Â Â Â Â Â Â r = amdgpu_bo_create_kernel(adev, bo_size, PAGE_SIZE,
> AMDGPU_GEM_DOMAIN_VRAM, &adev->vcn.vcpu_bo,
> &adev->vcn.gpu_addr, &adev->vcn.cpu_addr);
> @@ -189,11 +190,13 @@ int amdgpu_vcn_resume(struct amdgpu_device *adev)
> Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â unsigned offset;
>
> Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â hdr = (const struct common_firmware_header
> *)adev->vcn.fw->data;
> -Â Â Â Â Â Â Â Â Â Â Â Â Â Â offset = le32_to_cpu(hdr->ucode_array_offset_bytes);
> -Â Â Â Â Â Â Â Â Â Â Â Â Â Â memcpy_toio(adev->vcn.cpu_addr, adev->vcn.fw->data +
> offset,
> - le32_to_cpu(hdr->ucode_size_bytes));
> -Â Â Â Â Â Â Â Â Â Â Â Â Â Â size -= le32_to_cpu(hdr->ucode_size_bytes);
> -Â Â Â Â Â Â Â Â Â Â Â Â Â Â ptr += le32_to_cpu(hdr->ucode_size_bytes);
> +Â Â Â Â Â Â Â Â Â Â Â Â Â Â if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
> +Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â offset =
> le32_to_cpu(hdr->ucode_array_offset_bytes);
> +Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â memcpy_toio(adev->vcn.cpu_addr,
> adev->vcn.fw->data + offset,
> + le32_to_cpu(hdr->ucode_size_bytes));
> +Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â size -= le32_to_cpu(hdr->ucode_size_bytes);
> +Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â ptr += le32_to_cpu(hdr->ucode_size_bytes);
> +Â Â Â Â Â Â Â Â Â Â Â Â Â Â }
> Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â memset_io(ptr, 0, size);
> Â Â Â Â Â Â Â Â }
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
> b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
> index 2ce91a7..74c4ef4 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
> @@ -100,6 +100,16 @@ static int vcn_v1_0_sw_init(void *handle)
> Â Â Â Â Â Â Â Â if (r)
> Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â return r;
>
> +Â Â Â Â Â Â if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
> +Â Â Â Â Â Â Â Â Â Â Â Â Â Â const struct common_firmware_header *hdr;
> +Â Â Â Â Â Â Â Â Â Â Â Â Â Â hdr = (const struct common_firmware_header
> *)adev->vcn.fw->data;
> + adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].ucode_id =
> AMDGPU_UCODE_ID_VCN;
> + adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].fw = adev->vcn.fw;
> +Â Â Â Â Â Â Â Â Â Â Â Â Â Â adev->firmware.fw_size +=
> + ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE);
> +Â Â Â Â Â Â Â Â Â Â Â Â Â Â DRM_INFO("PSP loading VCN firmware\n");
> +Â Â Â Â Â Â }
> +
> Â Â Â Â Â Â Â Â r = amdgpu_vcn_resume(adev);
> Â Â Â Â Â Â Â Â if (r)
> Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â return r;
> @@ -265,26 +275,38 @@ static int vcn_v1_0_resume(void *handle)
> Â static void vcn_v1_0_mc_resume(struct amdgpu_device *adev)
> Â {
> Â Â Â Â Â Â Â Â uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4);
> -
> -Â Â Â Â Â Â WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
> +Â Â Â Â Â Â uint32_t offset;
> +
> +Â Â Â Â Â Â if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
> +Â Â Â Â Â Â Â Â Â Â Â Â Â Â WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
> + (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_lo));
> +Â Â Â Â Â Â Â Â Â Â Â Â Â Â WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
> + (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_hi));
> +Â Â Â Â Â Â Â Â Â Â Â Â Â Â WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 0);
> +Â Â Â Â Â Â Â Â Â Â Â Â Â Â offset = 0;
> +Â Â Â Â Â Â } else {
> +Â Â Â Â Â Â Â Â Â Â Â Â Â Â WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
> lower_32_bits(adev->vcn.gpu_addr));
> -Â Â Â Â Â Â WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
> +Â Â Â Â Â Â Â Â Â Â Â Â Â Â WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
> upper_32_bits(adev->vcn.gpu_addr));
> -Â Â Â Â Â Â WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0,
> +Â Â Â Â Â Â Â Â Â Â Â Â Â Â offset = size;
> +Â Â Â Â Â Â Â Â Â Â Â Â Â Â WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0,
> AMDGPU_UVD_FIRMWARE_OFFSET >> 3);
> +Â Â Â Â Â Â }
> +
> Â Â Â Â Â Â Â Â WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE0, size);
>
> Â Â Â Â Â Â Â Â WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW,
> - lower_32_bits(adev->vcn.gpu_addr + size));
> + lower_32_bits(adev->vcn.gpu_addr + offset));
> Â Â Â Â Â Â Â Â WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH,
> - upper_32_bits(adev->vcn.gpu_addr + size));
> + upper_32_bits(adev->vcn.gpu_addr + offset));
> Â Â Â Â Â Â Â Â WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET1, 0);
> Â Â Â Â Â Â Â Â WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE1,
> AMDGPU_VCN_HEAP_SIZE);
>
> Â Â Â Â Â Â Â Â WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW,
> - lower_32_bits(adev->vcn.gpu_addr + size + AMDGPU_VCN_HEAP_SIZE));
> + lower_32_bits(adev->vcn.gpu_addr + offset + AMDGPU_VCN_HEAP_SIZE));
> Â Â Â Â Â Â Â Â WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH,
> - upper_32_bits(adev->vcn.gpu_addr + size + AMDGPU_VCN_HEAP_SIZE));
> + upper_32_bits(adev->vcn.gpu_addr + offset + AMDGPU_VCN_HEAP_SIZE));
> Â Â Â Â Â Â Â Â WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET2, 0);
> Â Â Â Â Â Â Â Â WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE2,
> Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â AMDGPU_VCN_STACK_SIZE +
> (AMDGPU_VCN_SESSION_SIZE * 40));
> --
> 2.7.4
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx at lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
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