rs600_asic_reset() is never called in atomic context. They call mdelay() to busily wait, which is not necessary. mdelay() can be replaced with msleep() and usleep_range(). This is found by a static analysis tool named DCNS written by myself. Signed-off-by: Jia-Ju Bai <baijiaju1990 at gmail.com> --- drivers/gpu/drm/radeon/rs600.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/radeon/rs600.c b/drivers/gpu/drm/radeon/rs600.c index f16af119c688..1a97f5fd719b 100644 --- a/drivers/gpu/drm/radeon/rs600.c +++ b/drivers/gpu/drm/radeon/rs600.c @@ -472,30 +472,30 @@ int rs600_asic_reset(struct radeon_device *rdev, bool hard) pci_save_state(rdev->pdev); /* disable bus mastering */ pci_clear_master(rdev->pdev); - mdelay(1); + usleep_range(1000, 2000); /* reset GA+VAP */ WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_VAP(1) | S_0000F0_SOFT_RESET_GA(1)); RREG32(R_0000F0_RBBM_SOFT_RESET); - mdelay(500); + msleep(500); WREG32(R_0000F0_RBBM_SOFT_RESET, 0); - mdelay(1); + usleep_range(1000, 2000); status = RREG32(R_000E40_RBBM_STATUS); dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); /* reset CP */ WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1)); RREG32(R_0000F0_RBBM_SOFT_RESET); - mdelay(500); + msleep(500); WREG32(R_0000F0_RBBM_SOFT_RESET, 0); - mdelay(1); + usleep_range(1000, 2000); status = RREG32(R_000E40_RBBM_STATUS); dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); /* reset MC */ WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_MC(1)); RREG32(R_0000F0_RBBM_SOFT_RESET); - mdelay(500); + msleep(500); WREG32(R_0000F0_RBBM_SOFT_RESET, 0); - mdelay(1); + usleep_range(1000, 2000); status = RREG32(R_000E40_RBBM_STATUS); dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); /* restore PCI & busmastering */ -- 2.17.0
