On 2018-07-17 06:39 AM, Michel Dänzer wrote: > From: Michel Dänzer <michel.daenzer at amd.com> > > Allowing CONFIG_DRM_AMD_DC_DCN1_0 to be disabled on X86 was an > opportunity for display with Raven Ridge accidentally not working. > > Signed-off-by: Michel Dänzer <michel.daenzer at amd.com> Reviewed-by: Harry Wentland <harry.wentland at amd.com> Harry > --- > drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 +- > drivers/gpu/drm/amd/display/Kconfig | 8 -------- > .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 8 ++++---- > drivers/gpu/drm/amd/display/dc/Makefile | 2 +- > .../display/dc/bios/command_table_helper2.c | 2 +- > drivers/gpu/drm/amd/display/dc/calcs/Makefile | 2 +- > drivers/gpu/drm/amd/display/dc/core/dc.c | 6 +++--- > .../gpu/drm/amd/display/dc/core/dc_debug.c | 2 +- > .../gpu/drm/amd/display/dc/core/dc_resource.c | 12 +++++------ > drivers/gpu/drm/amd/display/dc/dc.h | 2 +- > .../drm/amd/display/dc/dce/dce_clock_source.c | 6 +++--- > .../drm/amd/display/dc/dce/dce_clock_source.h | 2 +- > .../gpu/drm/amd/display/dc/dce/dce_clocks.c | 8 ++++---- > .../gpu/drm/amd/display/dc/dce/dce_clocks.h | 2 +- > drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c | 6 +++--- > .../amd/display/dc/dce/dce_stream_encoder.c | 20 +++++++++---------- > .../display/dc/dce110/dce110_hw_sequencer.c | 2 +- > drivers/gpu/drm/amd/display/dc/gpio/Makefile | 2 +- > .../gpu/drm/amd/display/dc/gpio/hw_factory.c | 4 ++-- > .../drm/amd/display/dc/gpio/hw_translate.c | 4 ++-- > .../gpu/drm/amd/display/dc/i2caux/Makefile | 2 +- > .../gpu/drm/amd/display/dc/i2caux/i2caux.c | 4 ++-- > .../gpu/drm/amd/display/dc/inc/core_types.h | 6 +++--- > drivers/gpu/drm/amd/display/dc/irq/Makefile | 2 +- > .../gpu/drm/amd/display/dc/irq/irq_service.c | 2 +- > drivers/gpu/drm/amd/display/dc/os_types.h | 2 +- > 26 files changed, 56 insertions(+), 64 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c > index 709e4a386a0e..fb8c72851dfb 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c > @@ -2200,7 +2200,7 @@ bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type) > case CHIP_VEGA10: > case CHIP_VEGA12: > case CHIP_VEGA20: > -#if defined(CONFIG_DRM_AMD_DC_DCN1_0) > +#ifdef CONFIG_X86 > case CHIP_RAVEN: > #endif > return amdgpu_dc != 0; > diff --git a/drivers/gpu/drm/amd/display/Kconfig b/drivers/gpu/drm/amd/display/Kconfig > index 4c35625eb2c7..325083b0297e 100644 > --- a/drivers/gpu/drm/amd/display/Kconfig > +++ b/drivers/gpu/drm/amd/display/Kconfig > @@ -9,14 +9,6 @@ config DRM_AMD_DC > support for AMDGPU. This adds required support for Vega and > Raven ASICs. > > -config DRM_AMD_DC_DCN1_0 > - bool "DCN 1.0 Raven family" > - depends on DRM_AMD_DC && X86 > - default y > - help > - Choose this option if you want to have > - RV family for display engine > - > config DEBUG_KERNEL_DC > bool "Enable kgdb break in DC" > depends on DRM_AMD_DC > diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c > index 952691c6f81e..8e3ebd988043 100644 > --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c > +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c > @@ -58,7 +58,7 @@ > #include <drm/drm_fb_helper.h> > #include <drm/drm_edid.h> > > -#if defined(CONFIG_DRM_AMD_DC_DCN1_0) > +#ifdef CONFIG_X86 > #include "ivsrcid/irqsrcs_dcn_1_0.h" > > #include "dcn/dcn_1_0_offset.h" > @@ -1188,7 +1188,7 @@ static int dce110_register_irq_handlers(struct amdgpu_device *adev) > return 0; > } > > -#if defined(CONFIG_DRM_AMD_DC_DCN1_0) > +#ifdef CONFIG_X86 > /* Register IRQ sources and initialize IRQ callbacks */ > static int dcn10_register_irq_handlers(struct amdgpu_device *adev) > { > @@ -1522,7 +1522,7 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev) > goto fail; > } > break; > -#if defined(CONFIG_DRM_AMD_DC_DCN1_0) > +#ifdef CONFIG_X86 > case CHIP_RAVEN: > if (dcn10_register_irq_handlers(dm->adev)) { > DRM_ERROR("DM: Failed to initialize IRQ\n"); > @@ -1767,7 +1767,7 @@ static int dm_early_init(void *handle) > adev->mode_info.num_dig = 6; > adev->mode_info.plane_type = dm_plane_type_default; > break; > -#if defined(CONFIG_DRM_AMD_DC_DCN1_0) > +#ifdef CONFIG_X86 > case CHIP_RAVEN: > adev->mode_info.num_crtc = 4; > adev->mode_info.num_hpd = 4; > diff --git a/drivers/gpu/drm/amd/display/dc/Makefile b/drivers/gpu/drm/amd/display/dc/Makefile > index aed538a4d1ba..532a515fda9a 100644 > --- a/drivers/gpu/drm/amd/display/dc/Makefile > +++ b/drivers/gpu/drm/amd/display/dc/Makefile > @@ -25,7 +25,7 @@ > > DC_LIBS = basics bios calcs dce gpio i2caux irq virtual > > -ifdef CONFIG_DRM_AMD_DC_DCN1_0 > +ifdef CONFIG_X86 > DC_LIBS += dcn10 dml > endif > > diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c > index bbbcef566c55..770ff89ba7e1 100644 > --- a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c > +++ b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c > @@ -55,7 +55,7 @@ bool dal_bios_parser_init_cmd_tbl_helper2( > case DCE_VERSION_11_22: > *h = dal_cmd_tbl_helper_dce112_get_table2(); > return true; > -#if defined(CONFIG_DRM_AMD_DC_DCN1_0) > +#ifdef CONFIG_X86 > case DCN_VERSION_1_0: > *h = dal_cmd_tbl_helper_dce112_get_table2(); > return true; > diff --git a/drivers/gpu/drm/amd/display/dc/calcs/Makefile b/drivers/gpu/drm/amd/display/dc/calcs/Makefile > index 95f332ee3e7e..416500e51b8d 100644 > --- a/drivers/gpu/drm/amd/display/dc/calcs/Makefile > +++ b/drivers/gpu/drm/amd/display/dc/calcs/Makefile > @@ -38,7 +38,7 @@ CFLAGS_dcn_calc_math.o := $(calcs_ccflags) -Wno-tautological-compare > > BW_CALCS = dce_calcs.o bw_fixed.o custom_float.o > > -ifdef CONFIG_DRM_AMD_DC_DCN1_0 > +ifdef CONFIG_X86 > BW_CALCS += dcn_calcs.o dcn_calc_math.o dcn_calc_auto.o > endif > > diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c > index 8fbe5866012c..16a5114b9b4a 100644 > --- a/drivers/gpu/drm/amd/display/dc/core/dc.c > +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c > @@ -474,7 +474,7 @@ static void destruct(struct dc *dc) > kfree(dc->bw_dceip); > dc->bw_dceip = NULL; > > -#ifdef CONFIG_DRM_AMD_DC_DCN1_0 > +#ifdef CONFIG_X86 > kfree(dc->dcn_soc); > dc->dcn_soc = NULL; > > @@ -490,7 +490,7 @@ static bool construct(struct dc *dc, > struct dc_context *dc_ctx; > struct bw_calcs_dceip *dc_dceip; > struct bw_calcs_vbios *dc_vbios; > -#ifdef CONFIG_DRM_AMD_DC_DCN1_0 > +#ifdef CONFIG_X86 > struct dcn_soc_bounding_box *dcn_soc; > struct dcn_ip_params *dcn_ip; > #endif > @@ -512,7 +512,7 @@ static bool construct(struct dc *dc, > } > > dc->bw_vbios = dc_vbios; > -#ifdef CONFIG_DRM_AMD_DC_DCN1_0 > +#ifdef CONFIG_X86 > dcn_soc = kzalloc(sizeof(*dcn_soc), GFP_KERNEL); > if (!dcn_soc) { > dm_error("%s: failed to create dcn_soc\n", __func__); > diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c > index e1ebdf7b5eaf..caece7c13bc6 100644 > --- a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c > +++ b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c > @@ -348,7 +348,7 @@ void context_clock_trace( > struct dc *dc, > struct dc_state *context) > { > -#if defined(CONFIG_DRM_AMD_DC_DCN1_0) > +#ifdef CONFIG_X86 > DC_LOGGER_INIT(dc->ctx->logger); > CLOCK_TRACE("Current: dispclk_khz:%d max_dppclk_khz:%d dcfclk_khz:%d\n" > "dcfclk_deep_sleep_khz:%d fclk_khz:%d socclk_khz:%d\n", > diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c > index f92c3738d2a0..0b3a50e42bcb 100644 > --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c > +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c > @@ -41,7 +41,7 @@ > #include "dce100/dce100_resource.h" > #include "dce110/dce110_resource.h" > #include "dce112/dce112_resource.h" > -#if defined(CONFIG_DRM_AMD_DC_DCN1_0) > +#ifdef CONFIG_X86 > #include "dcn10/dcn10_resource.h" > #endif > #include "dce120/dce120_resource.h" > @@ -85,7 +85,7 @@ enum dce_version resource_parse_asic_id(struct hw_asic_id asic_id) > case FAMILY_AI: > dc_version = DCE_VERSION_12_0; > break; > -#if defined(CONFIG_DRM_AMD_DC_DCN1_0) > +#ifdef CONFIG_X86 > case FAMILY_RV: > dc_version = DCN_VERSION_1_0; > break; > @@ -136,7 +136,7 @@ struct resource_pool *dc_create_resource_pool( > num_virtual_links, dc); > break; > > -#if defined(CONFIG_DRM_AMD_DC_DCN1_0) > +#ifdef CONFIG_X86 > case DCN_VERSION_1_0: > res_pool = dcn10_create_resource_pool( > num_virtual_links, dc); > @@ -1213,7 +1213,7 @@ static struct pipe_ctx *acquire_free_pipe_for_stream( > > } > > -#if defined(CONFIG_DRM_AMD_DC_DCN1_0) > +#ifdef CONFIG_X86 > static int acquire_first_split_pipe( > struct resource_context *res_ctx, > const struct resource_pool *pool, > @@ -1284,7 +1284,7 @@ bool dc_add_plane_to_context( > > free_pipe = acquire_free_pipe_for_stream(context, pool, stream); > > -#if defined(CONFIG_DRM_AMD_DC_DCN1_0) > +#ifdef CONFIG_X86 > if (!free_pipe) { > int pipe_idx = acquire_first_split_pipe(&context->res_ctx, pool, stream); > if (pipe_idx >= 0) > @@ -1902,7 +1902,7 @@ enum dc_status resource_map_pool_resources( > /* acquire new resources */ > pipe_idx = acquire_first_free_pipe(&context->res_ctx, pool, stream); > > -#ifdef CONFIG_DRM_AMD_DC_DCN1_0 > +#ifdef CONFIG_X86 > if (pipe_idx < 0) > pipe_idx = acquire_first_split_pipe(&context->res_ctx, pool, stream); > #endif > diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h > index b6d74e8c8deb..47f09f4fa217 100644 > --- a/drivers/gpu/drm/amd/display/dc/dc.h > +++ b/drivers/gpu/drm/amd/display/dc/dc.h > @@ -290,7 +290,7 @@ struct dc { > /* Inputs into BW and WM calculations. */ > struct bw_calcs_dceip *bw_dceip; > struct bw_calcs_vbios *bw_vbios; > -#ifdef CONFIG_DRM_AMD_DC_DCN1_0 > +#ifdef CONFIG_X86 > struct dcn_soc_bounding_box *dcn_soc; > struct dcn_ip_params *dcn_ip; > struct display_mode_lib dml; > diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c > index ca137757a69e..439dcf3b596c 100644 > --- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c > +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c > @@ -592,7 +592,7 @@ static uint32_t dce110_get_pix_clk_dividers( > case DCE_VERSION_11_2: > case DCE_VERSION_11_22: > case DCE_VERSION_12_0: > -#if defined(CONFIG_DRM_AMD_DC_DCN1_0) > +#ifdef CONFIG_X86 > case DCN_VERSION_1_0: > #endif > > @@ -909,7 +909,7 @@ static bool dce110_program_pix_clk( > struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(clock_source); > struct bp_pixel_clock_parameters bp_pc_params = {0}; > > -#if defined(CONFIG_DRM_AMD_DC_DCN1_0) > +#ifdef CONFIG_X86 > if (IS_FPGA_MAXIMUS_DC(clock_source->ctx->dce_environment)) { > unsigned int inst = pix_clk_params->controller_id - CONTROLLER_ID_D0; > unsigned dp_dto_ref_kHz = 700000; > @@ -982,7 +982,7 @@ static bool dce110_program_pix_clk( > case DCE_VERSION_11_2: > case DCE_VERSION_11_22: > case DCE_VERSION_12_0: > -#if defined(CONFIG_DRM_AMD_DC_DCN1_0) > +#ifdef CONFIG_X86 > case DCN_VERSION_1_0: > #endif > > diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h > index c45e2f76189e..801bb65707b3 100644 > --- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h > +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h > @@ -55,7 +55,7 @@ > CS_SF(PHYPLLA_PIXCLK_RESYNC_CNTL, PHYPLLA_DCCG_DEEP_COLOR_CNTL, mask_sh),\ > CS_SF(PHYPLLA_PIXCLK_RESYNC_CNTL, PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE, mask_sh) > > -#if defined(CONFIG_DRM_AMD_DC_DCN1_0) > +#ifdef CONFIG_X86 > > #define CS_COMMON_REG_LIST_DCN1_0(index, pllid) \ > SRI(PIXCLK_RESYNC_CNTL, PHYPLL, pllid),\ > diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c > index 6882dc953a2c..8f8a2abac3f3 100644 > --- a/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c > +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c > @@ -30,7 +30,7 @@ > #include "bios_parser_interface.h" > #include "dc.h" > #include "dmcu.h" > -#if defined(CONFIG_DRM_AMD_DC_DCN1_0) > +#ifdef CONFIG_X86 > #include "dcn_calcs.h" > #endif > #include "core_types.h" > @@ -478,7 +478,7 @@ static void dce12_update_clocks(struct dccg *dccg, > } > } > > -#ifdef CONFIG_DRM_AMD_DC_DCN1_0 > +#ifdef CONFIG_X86 > static int dcn1_determine_dppclk_threshold(struct dccg *dccg, struct dc_clocks *new_clocks) > { > bool request_dpp_div = new_clocks->dispclk_khz > new_clocks->dppclk_khz; > @@ -666,7 +666,7 @@ static void dce_update_clocks(struct dccg *dccg, > } > } > > -#ifdef CONFIG_DRM_AMD_DC_DCN1_0 > +#ifdef CONFIG_X86 > static const struct display_clock_funcs dcn1_funcs = { > .get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz, > .set_dispclk = dce112_set_clock, > @@ -821,7 +821,7 @@ struct dccg *dce120_dccg_create(struct dc_context *ctx) > return &clk_dce->base; > } > > -#ifdef CONFIG_DRM_AMD_DC_DCN1_0 > +#ifdef CONFIG_X86 > struct dccg *dcn1_dccg_create(struct dc_context *ctx) > { > struct dc_debug *debug = &ctx->dc->debug; > diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.h b/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.h > index 8a6b2d328467..e5e44adc6c27 100644 > --- a/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.h > +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.h > @@ -111,7 +111,7 @@ struct dccg *dce112_dccg_create( > > struct dccg *dce120_dccg_create(struct dc_context *ctx); > > -#ifdef CONFIG_DRM_AMD_DC_DCN1_0 > +#ifdef CONFIG_X86 > struct dccg *dcn1_dccg_create(struct dc_context *ctx); > #endif > > diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c b/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c > index a576b8bbb3cd..062a46543887 100644 > --- a/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c > +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c > @@ -314,7 +314,7 @@ static void dce_get_psr_wait_loop( > return; > } > > -#if defined(CONFIG_DRM_AMD_DC_DCN1_0) > +#ifdef CONFIG_X86 > static void dcn10_get_dmcu_state(struct dmcu *dmcu) > { > struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); > @@ -735,7 +735,7 @@ static const struct dmcu_funcs dce_funcs = { > .is_dmcu_initialized = dce_is_dmcu_initialized > }; > > -#if defined(CONFIG_DRM_AMD_DC_DCN1_0) > +#ifdef CONFIG_X86 > static const struct dmcu_funcs dcn10_funcs = { > .dmcu_init = dcn10_dmcu_init, > .load_iram = dcn10_dmcu_load_iram, > @@ -787,7 +787,7 @@ struct dmcu *dce_dmcu_create( > return &dmcu_dce->base; > } > > -#if defined(CONFIG_DRM_AMD_DC_DCN1_0) > +#ifdef CONFIG_X86 > struct dmcu *dcn10_dmcu_create( > struct dc_context *ctx, > const struct dce_dmcu_registers *regs, > diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c > index 91642e684858..b139b4017820 100644 > --- a/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c > +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c > @@ -135,7 +135,7 @@ static void dce110_update_generic_info_packet( > AFMT_GENERIC0_UPDATE, (packet_index == 0), > AFMT_GENERIC2_UPDATE, (packet_index == 2)); > } > -#if defined(CONFIG_DRM_AMD_DC_DCN1_0) > +#ifdef CONFIG_X86 > if (REG(AFMT_VBI_PACKET_CONTROL1)) { > switch (packet_index) { > case 0: > @@ -229,7 +229,7 @@ static void dce110_update_hdmi_info_packet( > HDMI_GENERIC1_SEND, send, > HDMI_GENERIC1_LINE, line); > break; > -#if defined(CONFIG_DRM_AMD_DC_DCN1_0) > +#ifdef CONFIG_X86 > case 4: > if (REG(HDMI_GENERIC_PACKET_CONTROL2)) > REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL2, > @@ -274,7 +274,7 @@ static void dce110_stream_encoder_dp_set_stream_attribute( > struct dc_crtc_timing *crtc_timing, > enum dc_color_space output_color_space) > { > -#if defined(CONFIG_DRM_AMD_DC_DCN1_0) > +#ifdef CONFIG_X86 > uint32_t h_active_start; > uint32_t v_active_start; > uint32_t misc0 = 0; > @@ -317,7 +317,7 @@ static void dce110_stream_encoder_dp_set_stream_attribute( > if (enc110->se_mask->DP_VID_M_DOUBLE_VALUE_EN) > REG_UPDATE(DP_VID_TIMING, DP_VID_M_DOUBLE_VALUE_EN, 1); > > -#if defined(CONFIG_DRM_AMD_DC_DCN1_0) > +#ifdef CONFIG_X86 > if (enc110->se_mask->DP_VID_N_MUL) > REG_UPDATE(DP_VID_TIMING, DP_VID_N_MUL, 1); > #endif > @@ -328,7 +328,7 @@ static void dce110_stream_encoder_dp_set_stream_attribute( > break; > } > > -#if defined(CONFIG_DRM_AMD_DC_DCN1_0) > +#ifdef CONFIG_X86 > if (REG(DP_MSA_MISC)) > misc1 = REG_READ(DP_MSA_MISC); > #endif > @@ -362,7 +362,7 @@ static void dce110_stream_encoder_dp_set_stream_attribute( > /* set dynamic range and YCbCr range */ > > > -#if defined(CONFIG_DRM_AMD_DC_DCN1_0) > +#ifdef CONFIG_X86 > switch (crtc_timing->display_color_depth) { > case COLOR_DEPTH_666: > colorimetry_bpc = 0; > @@ -441,7 +441,7 @@ static void dce110_stream_encoder_dp_set_stream_attribute( > DP_DYN_RANGE, dynamic_range_rgb, > DP_YCBCR_RANGE, dynamic_range_ycbcr); > > -#if defined(CONFIG_DRM_AMD_DC_DCN1_0) > +#ifdef CONFIG_X86 > if (REG(DP_MSA_COLORIMETRY)) > REG_SET(DP_MSA_COLORIMETRY, 0, DP_MSA_MISC0, misc0); > > @@ -476,7 +476,7 @@ static void dce110_stream_encoder_dp_set_stream_attribute( > crtc_timing->v_front_porch; > > > -#if defined(CONFIG_DRM_AMD_DC_DCN1_0) > +#ifdef CONFIG_X86 > /* start at begining of left border */ > if (REG(DP_MSA_TIMING_PARAM2)) > REG_SET_2(DP_MSA_TIMING_PARAM2, 0, > @@ -751,7 +751,7 @@ static void dce110_stream_encoder_update_hdmi_info_packets( > dce110_update_hdmi_info_packet(enc110, 3, &info_frame->hdrsmd); > } > > -#if defined(CONFIG_DRM_AMD_DC_DCN1_0) > +#ifdef CONFIG_X86 > if (enc110->se_mask->HDMI_DB_DISABLE) { > /* for bring up, disable dp double TODO */ > if (REG(HDMI_DB_CONTROL)) > @@ -789,7 +789,7 @@ static void dce110_stream_encoder_stop_hdmi_info_packets( > HDMI_GENERIC1_LINE, 0, > HDMI_GENERIC1_SEND, 0); > > -#if defined(CONFIG_DRM_AMD_DC_DCN1_0) > +#ifdef CONFIG_X86 > /* stop generic packets 2 & 3 on HDMI */ > if (REG(HDMI_GENERIC_PACKET_CONTROL2)) > REG_SET_6(HDMI_GENERIC_PACKET_CONTROL2, 0, > diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c > index 2202c1716a1b..e0444497cbf9 100644 > --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c > +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c > @@ -1250,7 +1250,7 @@ static void program_scaler(const struct dc *dc, > { > struct tg_color color = {0}; > > -#if defined(CONFIG_DRM_AMD_DC_DCN1_0) > +#ifdef CONFIG_X86 > /* TOFPGA */ > if (pipe_ctx->plane_res.xfm->funcs->transform_set_pixel_storage_depth == NULL) > return; > diff --git a/drivers/gpu/drm/amd/display/dc/gpio/Makefile b/drivers/gpu/drm/amd/display/dc/gpio/Makefile > index 562ee189d780..b9d9930a4974 100644 > --- a/drivers/gpu/drm/amd/display/dc/gpio/Makefile > +++ b/drivers/gpu/drm/amd/display/dc/gpio/Makefile > @@ -61,7 +61,7 @@ AMD_DISPLAY_FILES += $(AMD_DAL_GPIO_DCE120) > ############################################################################### > # DCN 1x > ############################################################################### > -ifdef CONFIG_DRM_AMD_DC_DCN1_0 > +ifdef CONFIG_X86 > GPIO_DCN10 = hw_translate_dcn10.o hw_factory_dcn10.o > > AMD_DAL_GPIO_DCN10 = $(addprefix $(AMDDALPATH)/dc/gpio/dcn10/,$(GPIO_DCN10)) > diff --git a/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c b/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c > index 0caee3523017..83df779984e5 100644 > --- a/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c > +++ b/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c > @@ -43,7 +43,7 @@ > #include "dce80/hw_factory_dce80.h" > #include "dce110/hw_factory_dce110.h" > #include "dce120/hw_factory_dce120.h" > -#if defined(CONFIG_DRM_AMD_DC_DCN1_0) > +#ifdef CONFIG_X86 > #include "dcn10/hw_factory_dcn10.h" > #endif > > @@ -81,7 +81,7 @@ bool dal_hw_factory_init( > case DCE_VERSION_12_0: > dal_hw_factory_dce120_init(factory); > return true; > -#if defined(CONFIG_DRM_AMD_DC_DCN1_0) > +#ifdef CONFIG_X86 > case DCN_VERSION_1_0: > dal_hw_factory_dcn10_init(factory); > return true; > diff --git a/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c b/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c > index 55c707488541..e7541310480b 100644 > --- a/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c > +++ b/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c > @@ -43,7 +43,7 @@ > #include "dce80/hw_translate_dce80.h" > #include "dce110/hw_translate_dce110.h" > #include "dce120/hw_translate_dce120.h" > -#if defined(CONFIG_DRM_AMD_DC_DCN1_0) > +#ifdef CONFIG_X86 > #include "dcn10/hw_translate_dcn10.h" > #endif > > @@ -78,7 +78,7 @@ bool dal_hw_translate_init( > case DCE_VERSION_12_0: > dal_hw_translate_dce120_init(translate); > return true; > -#if defined(CONFIG_DRM_AMD_DC_DCN1_0) > +#ifdef CONFIG_X86 > case DCN_VERSION_1_0: > dal_hw_translate_dcn10_init(translate); > return true; > diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/Makefile b/drivers/gpu/drm/amd/display/dc/i2caux/Makefile > index 352885cb4d07..a851d07f0190 100644 > --- a/drivers/gpu/drm/amd/display/dc/i2caux/Makefile > +++ b/drivers/gpu/drm/amd/display/dc/i2caux/Makefile > @@ -71,7 +71,7 @@ AMD_DISPLAY_FILES += $(AMD_DAL_I2CAUX_DCE112) > ############################################################################### > # DCN 1.0 family > ############################################################################### > -ifdef CONFIG_DRM_AMD_DC_DCN1_0 > +ifdef CONFIG_X86 > I2CAUX_DCN1 = i2caux_dcn10.o > > AMD_DAL_I2CAUX_DCN1 = $(addprefix $(AMDDALPATH)/dc/i2caux/dcn10/,$(I2CAUX_DCN1)) > diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/i2caux.c b/drivers/gpu/drm/amd/display/dc/i2caux/i2caux.c > index 9b0bcc6b769b..f7ed355fc84f 100644 > --- a/drivers/gpu/drm/amd/display/dc/i2caux/i2caux.c > +++ b/drivers/gpu/drm/amd/display/dc/i2caux/i2caux.c > @@ -59,7 +59,7 @@ > > #include "dce120/i2caux_dce120.h" > > -#if defined(CONFIG_DRM_AMD_DC_DCN1_0) > +#ifdef CONFIG_X86 > #include "dcn10/i2caux_dcn10.h" > #endif > > @@ -91,7 +91,7 @@ struct i2caux *dal_i2caux_create( > return dal_i2caux_dce100_create(ctx); > case DCE_VERSION_12_0: > return dal_i2caux_dce120_create(ctx); > -#if defined(CONFIG_DRM_AMD_DC_DCN1_0) > +#ifdef CONFIG_X86 > case DCN_VERSION_1_0: > return dal_i2caux_dcn10_create(ctx); > #endif > diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h > index 1db26bc0bec3..4446652a9a9e 100644 > --- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h > +++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h > @@ -33,7 +33,7 @@ > #include "dc_bios_types.h" > #include "mem_input.h" > #include "hubp.h" > -#if defined(CONFIG_DRM_AMD_DC_DCN1_0) > +#ifdef CONFIG_X86 > #include "mpc.h" > #endif > > @@ -221,7 +221,7 @@ struct pipe_ctx { > struct pipe_ctx *top_pipe; > struct pipe_ctx *bottom_pipe; > > -#ifdef CONFIG_DRM_AMD_DC_DCN1_0 > +#ifdef CONFIG_X86 > struct _vcs_dpi_display_dlg_regs_st dlg_regs; > struct _vcs_dpi_display_ttu_regs_st ttu_regs; > struct _vcs_dpi_display_rq_regs_st rq_regs; > @@ -276,7 +276,7 @@ struct dc_state { > > /* Note: these are big structures, do *not* put on stack! */ > struct dm_pp_display_configuration pp_display_cfg; > -#ifdef CONFIG_DRM_AMD_DC_DCN1_0 > +#ifdef CONFIG_X86 > struct dcn_bw_internal_vars dcn_bw_vars; > #endif > > diff --git a/drivers/gpu/drm/amd/display/dc/irq/Makefile b/drivers/gpu/drm/amd/display/dc/irq/Makefile > index 498515aad4a5..a76ee600ecee 100644 > --- a/drivers/gpu/drm/amd/display/dc/irq/Makefile > +++ b/drivers/gpu/drm/amd/display/dc/irq/Makefile > @@ -60,7 +60,7 @@ AMD_DISPLAY_FILES += $(AMD_DAL_IRQ_DCE12) > ############################################################################### > # DCN 1x > ############################################################################### > -ifdef CONFIG_DRM_AMD_DC_DCN1_0 > +ifdef CONFIG_X86 > IRQ_DCN1 = irq_service_dcn10.o > > AMD_DAL_IRQ_DCN1 = $(addprefix $(AMDDALPATH)/dc/irq/dcn10/,$(IRQ_DCN1)) > diff --git a/drivers/gpu/drm/amd/display/dc/irq/irq_service.c b/drivers/gpu/drm/amd/display/dc/irq/irq_service.c > index 604bea01fc13..ae3fd0a235ba 100644 > --- a/drivers/gpu/drm/amd/display/dc/irq/irq_service.c > +++ b/drivers/gpu/drm/amd/display/dc/irq/irq_service.c > @@ -36,7 +36,7 @@ > #include "dce120/irq_service_dce120.h" > > > -#if defined(CONFIG_DRM_AMD_DC_DCN1_0) > +#ifdef CONFIG_X86 > #include "dcn10/irq_service_dcn10.h" > #endif > > diff --git a/drivers/gpu/drm/amd/display/dc/os_types.h b/drivers/gpu/drm/amd/display/dc/os_types.h > index a407892905af..c9fce9066ad8 100644 > --- a/drivers/gpu/drm/amd/display/dc/os_types.h > +++ b/drivers/gpu/drm/amd/display/dc/os_types.h > @@ -48,7 +48,7 @@ > > #define dm_error(fmt, ...) DRM_ERROR(fmt, ##__VA_ARGS__) > > -#if defined(CONFIG_DRM_AMD_DC_DCN1_0) > +#ifdef CONFIG_X86 > #include <asm/fpu/api.h> > #endif > >