On Tue, Jul 17, 2018 at 12:22 PM, Michel Dänzer <michel at daenzer.net> wrote:
> From: Michel Dänzer <michel.daenzer at amd.com>
>
> Only supported with the advanced colour management properties available
> with DC as of kernel 4.17.
>
> Signed-off-by: Michel Dänzer <michel.daenzer at amd.com>
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
> ---
> src/drmmode_display.c | 47 +++++++++++++++++++++++++++++++------------
> 1 file changed, 34 insertions(+), 13 deletions(-)
>
> diff --git a/src/drmmode_display.c b/src/drmmode_display.c
> index f6cafccdc..f5ab7955e 100644
> --- a/src/drmmode_display.c
> +++ b/src/drmmode_display.c
> @@ -3333,14 +3333,14 @@ Bool drmmode_pre_init(ScrnInfoPtr pScrn, drmmode_ptr drmmode, int cpp)
> info->drmmode_crtc_funcs.shadow_destroy = NULL;
> }
>
> + drmmode_cm_init(pAMDGPUEnt->fd, drmmode, mode_res);
> +
> /* Hw gamma lut's are currently bypassed by the hw at color depth 30,
> * so spare the server the effort to compute and update the cluts.
> */
> - if (pScrn->depth == 30)
> + if (pScrn->depth == 30 && !drmmode_cm_enabled(drmmode))
> info->drmmode_crtc_funcs.gamma_set = NULL;
>
> - drmmode_cm_init(pAMDGPUEnt->fd, drmmode, mode_res);
> -
> for (i = 0; i < mode_res->count_crtcs; i++)
> if (!xf86IsEntityShared(pScrn->entityList[0]) ||
> (crtcs_needed && !(pAMDGPUEnt->assigned_crtcs & (1 << i))))
> @@ -3636,29 +3636,50 @@ Bool drmmode_set_desired_modes(ScrnInfoPtr pScrn, drmmode_ptr drmmode,
> Bool drmmode_setup_colormap(ScreenPtr pScreen, ScrnInfoPtr pScrn)
> {
> xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
> + AMDGPUInfoPtr info = AMDGPUPTR(pScrn);
> int i;
>
> if (xf86_config->num_crtc) {
> xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, AMDGPU_LOGLEVEL_DEBUG,
> "Initializing kms color map\n");
> +
> if (!miCreateDefColormap(pScreen))
> return FALSE;
> - /* All radeons support 10 bit CLUTs. They get bypassed at depth 30. */
> - if (pScrn->depth != 30) {
> - if (!xf86HandleColormaps(pScreen, 256, 10, NULL, NULL,
> - CMAP_PALETTED_TRUECOLOR
> - | CMAP_RELOAD_ON_MODE_SWITCH))
> - return FALSE;
> +
> + if (pScrn->depth == 30) {
> + if (!drmmode_cm_enabled(&info->drmmode))
> + return TRUE;
>
> for (i = 0; i < xf86_config->num_crtc; i++) {
> xf86CrtcPtr crtc = xf86_config->crtc[i];
> + void *gamma = malloc(1024 * 3 * sizeof(CARD16));
> +
> + if (!gamma) {
> + ErrorF("Failed to allocate gamma LUT memory\n");
> + return FALSE;
> + }
>
> - drmmode_crtc_gamma_do_set(crtc, crtc->gamma_red,
> - crtc->gamma_green,
> - crtc->gamma_blue,
> - crtc->gamma_size);
> + crtc->gamma_size = 1024;
> + crtc->gamma_red = gamma;
> + crtc->gamma_green = crtc->gamma_red + crtc->gamma_size;
> + crtc->gamma_blue = crtc->gamma_green + crtc->gamma_size;
> }
> }
> +
> + /* All Radeons support 10 bit CLUTs. */
> + if (!xf86HandleColormaps(pScreen, 1 << pScrn->rgbBits, 10,
> + NULL, NULL, CMAP_PALETTED_TRUECOLOR
> + | CMAP_RELOAD_ON_MODE_SWITCH))
> + return FALSE;
> +
> + for (i = 0; i < xf86_config->num_crtc; i++) {
> + xf86CrtcPtr crtc = xf86_config->crtc[i];
> +
> + drmmode_crtc_gamma_do_set(crtc, crtc->gamma_red,
> + crtc->gamma_green,
> + crtc->gamma_blue,
> + crtc->gamma_size);
> + }
> }
>
> return TRUE;
> --
> 2.18.0
>
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