On Thu, Jul 05, 2018 at 11:33:52AM -0400, Alex Deucher wrote: > On Thu, Jul 5, 2018 at 5:09 AM, Evan Quan <evan.quan at amd.com> wrote: > > This may break gfxoff support since this register will > > be set by smc fw(for vega12, that's the case). > > > > It took me a second to understand what you meant here. Might be > worthwhile to clarify with something like: > SMU owns this register so the driver should not set it to avoid breaking gfxoff. > Agree. Actually, it cleared Ultra_Low_Voltage_Enable bit of mmRLC_PG_CNTL, that caused gfxoff break before. We should have explained clearly here. :-) Thanks, Ray > With that fixed up: > Reviewed-by: Alex Deucher <alexander.deucher at amd.com> > > Alex > > > Change-Id: Id3108c63634a2f941289021bfbd78588c0f6c4d6 > > Signed-off-by: Evan Quan <evan.quan at amd.com> > > --- > > drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 3 --- > > 1 file changed, 3 deletions(-) > > > > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c > > index 8d870d4f8414..3a75641a071d 100644 > > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c > > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c > > @@ -2290,9 +2290,6 @@ static int gfx_v9_0_rlc_resume(struct amdgpu_device *adev) > > /* disable CG */ > > WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0); > > > > - /* disable PG */ > > - WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, 0); > > - > > gfx_v9_0_rlc_reset(adev); > > > > gfx_v9_0_init_pg(adev); > > -- > > 2.18.0 > > > > _______________________________________________ > > amd-gfx mailing list > > amd-gfx at lists.freedesktop.org > > https://lists.freedesktop.org/mailman/listinfo/amd-gfx > _______________________________________________ > amd-gfx mailing list > amd-gfx at lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx
