From: Michel Dänzer <michel.daenzer@xxxxxxx>
Signed-off-by: Michel Dänzer <michel.daenzer at amd.com>
---
src/drmmode_display.c | 16 +++-------------
src/radeon.h | 1 +
src/radeon_bo_helper.c | 10 ++++++++++
src/radeon_bo_helper.h | 3 +++
src/radeon_glamor_wrappers.c | 21 ++++++++++-----------
src/radeon_kms.c | 6 ++----
src/radeon_present.c | 4 +---
7 files changed, 30 insertions(+), 31 deletions(-)
diff --git a/src/drmmode_display.c b/src/drmmode_display.c
index 54b09730d..3c4d94fd9 100644
--- a/src/drmmode_display.c
+++ b/src/drmmode_display.c
@@ -726,8 +726,7 @@ drmmode_crtc_prime_scanout_update(xf86CrtcPtr crtc, DisplayModePtr mode,
gc, 0, 0, mode->HDisplay, mode->VDisplay,
0, 0);
FreeScratchGC(gc);
- radeon_cs_flush_indirect(scrn);
- radeon_bo_wait(drmmode_crtc->scanout[0].bo);
+ radeon_finish(scrn, drmmode_crtc->scanout[0].bo);
}
}
@@ -785,8 +784,7 @@ drmmode_crtc_scanout_update(xf86CrtcPtr crtc, DisplayModePtr mode,
radeon_scanout_do_update(crtc, scanout_id,
screen->GetWindowPixmap(screen->root),
*box);
- radeon_cs_flush_indirect(scrn);
- radeon_bo_wait(drmmode_crtc->scanout[scanout_id].bo);
+ radeon_finish(scrn, drmmode_crtc->scanout[scanout_id].bo);
}
}
@@ -2240,7 +2238,6 @@ drmmode_xf86crtc_resize (ScrnInfoPtr scrn, int width, int height)
int aligned_height;
uint32_t screen_size;
int cpp = info->pixel_bytes;
- struct radeon_bo *front_bo;
struct radeon_surface surface;
uint32_t tiling_flags = 0, base_align;
PixmapPtr ppix = screen->GetScreenPixmap(screen);
@@ -2249,12 +2246,6 @@ drmmode_xf86crtc_resize (ScrnInfoPtr scrn, int width, int height)
if (scrn->virtualX == width && scrn->virtualY == height)
return TRUE;
- front_bo = info->front_bo;
- radeon_cs_flush_indirect(scrn);
-
- if (front_bo)
- radeon_bo_wait(front_bo);
-
if (info->allowColorTiling && !info->shadow_primary) {
if (info->ChipFamily >= CHIP_FAMILY_R600) {
if (info->allowColorTiling2D) {
@@ -2364,8 +2355,7 @@ drmmode_xf86crtc_resize (ScrnInfoPtr scrn, int width, int height)
}
radeon_pixmap_clear(ppix);
- radeon_cs_flush_indirect(scrn);
- radeon_bo_wait(info->front_bo);
+ radeon_finish(scrn, info->front_bo);
for (i = 0; i < xf86_config->num_crtc; i++) {
xf86CrtcPtr crtc = xf86_config->crtc[i];
diff --git a/src/radeon.h b/src/radeon.h
index c2ae6606e..499e89f92 100644
--- a/src/radeon.h
+++ b/src/radeon.h
@@ -895,6 +895,7 @@ radeon_pixmap_get_fb(PixmapPtr pix)
return *fb_ptr;
}
+
#define CP_PACKET0(reg, n) \
(RADEON_CP_PACKET0 | ((n) << 16) | ((reg) >> 2))
#define CP_PACKET1(reg0, reg1) \
diff --git a/src/radeon_bo_helper.c b/src/radeon_bo_helper.c
index 376589427..7cfe91265 100644
--- a/src/radeon_bo_helper.c
+++ b/src/radeon_bo_helper.c
@@ -235,6 +235,16 @@ radeon_alloc_pixmap_bo(ScrnInfoPtr pScrn, int width, int height, int depth,
return bo;
}
+
+/* Flush and wait for the BO to become idle */
+void
+radeon_finish(ScrnInfoPtr scrn, struct radeon_bo *bo)
+{
+ radeon_cs_flush_indirect(scrn);
+ radeon_bo_wait(bo);
+}
+
+
/* Clear the pixmap contents to black */
void
radeon_pixmap_clear(PixmapPtr pixmap)
diff --git a/src/radeon_bo_helper.h b/src/radeon_bo_helper.h
index e1856adb1..fa99201b2 100644
--- a/src/radeon_bo_helper.h
+++ b/src/radeon_bo_helper.h
@@ -28,6 +28,9 @@ radeon_alloc_pixmap_bo(ScrnInfoPtr pScrn, int width, int height, int depth,
int usage_hint, int bitsPerPixel, int *new_pitch,
struct radeon_surface *new_surface, uint32_t *new_tiling);
+extern void
+radeon_finish(ScrnInfoPtr scrn, struct radeon_bo *bo);
+
extern void
radeon_pixmap_clear(PixmapPtr pixmap);
diff --git a/src/radeon_glamor_wrappers.c b/src/radeon_glamor_wrappers.c
index d73742528..94700a7b9 100644
--- a/src/radeon_glamor_wrappers.c
+++ b/src/radeon_glamor_wrappers.c
@@ -58,13 +58,13 @@ radeon_glamor_prepare_access_cpu(ScrnInfoPtr scrn, RADEONInfoPtr info,
struct radeon_bo *bo = priv->bo;
int ret;
- /* When falling back to swrast, flush all pending operations */
- if (need_sync) {
- glamor_block_handler(scrn->pScreen);
- info->gpu_flushed++;
- }
-
if (!pixmap->devPrivate.ptr) {
+ /* When falling back to swrast, flush all pending operations */
+ if (need_sync) {
+ glamor_block_handler(scrn->pScreen);
+ info->gpu_flushed++;
+ }
+
ret = radeon_bo_map(bo, 1);
if (ret) {
xf86DrvMsg(scrn->scrnIndex, X_WARNING,
@@ -76,11 +76,10 @@ radeon_glamor_prepare_access_cpu(ScrnInfoPtr scrn, RADEONInfoPtr info,
}
pixmap->devPrivate.ptr = bo->ptr;
- info->gpu_synced = info->gpu_flushed;
- } else if (need_sync) {
- radeon_bo_wait(bo);
- info->gpu_synced = info->gpu_flushed;
- }
+ } else if (need_sync)
+ radeon_finish(scrn, bo);
+
+ info->gpu_synced = info->gpu_flushed;
return TRUE;
}
diff --git a/src/radeon_kms.c b/src/radeon_kms.c
index 8579aaf81..d4b59e81b 100644
--- a/src/radeon_kms.c
+++ b/src/radeon_kms.c
@@ -1681,8 +1681,7 @@ void RADEONWindowExposures_oneshot(WindowPtr pWin, RegionPtr pRegion
pScreen->WindowExposures(pWin, pRegion);
#endif
- radeon_cs_flush_indirect(pScrn);
- radeon_bo_wait(info->front_bo);
+ radeon_finish(pScrn, info->front_bo);
drmmode_set_desired_modes(pScrn, &info->drmmode, TRUE);
}
@@ -2585,8 +2584,7 @@ void RADEONLeaveVT_KMS(ScrnInfoPtr pScrn)
radeon_pixmap_get_fb(black_scanout.pixmap);
radeon_pixmap_clear(black_scanout.pixmap);
- radeon_cs_flush_indirect(pScrn);
- radeon_bo_wait(black_scanout.bo);
+ radeon_finish(pScrn, black_scanout.bo);
for (i = 0; i < xf86_config->num_crtc; i++) {
crtc = xf86_config->crtc[i];
diff --git a/src/radeon_present.c b/src/radeon_present.c
index d734b9d44..66805d7df 100644
--- a/src/radeon_present.c
+++ b/src/radeon_present.c
@@ -404,8 +404,6 @@ radeon_present_unflip(ScreenPtr screen, uint64_t event_id)
FLIP_ASYNC : FLIP_VSYNC;
int i;
- radeon_cs_flush_indirect(scrn);
-
if (!radeon_present_check_unflip(scrn))
goto modeset;
@@ -424,7 +422,7 @@ radeon_present_unflip(ScreenPtr screen, uint64_t event_id)
return;
modeset:
- radeon_bo_wait(info->front_bo);
+ radeon_finish(scrn, info->front_bo);
for (i = 0; i < config->num_crtc; i++) {
xf86CrtcPtr crtc = config->crtc[i];
drmmode_crtc_private_ptr drmmode_crtc = crtc->driver_private;
--
2.18.0
