powerplay can notify smu to recalculates the maximum deep-sleep divider that display allowed. Signed-off-by: Rex Zhu <Rex.Zhu at amd.com> --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c index 50e8630..2e6518f 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c @@ -454,10 +454,21 @@ void pp_rv_set_display_requirement(struct pp_smu *pp, struct dc_context *ctx = pp->ctx; struct amdgpu_device *adev = ctx->driver_context; const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs; + void *pp_handle = adev->powerplay.pp_handle; + struct pp_display_clock_request request; - if (!pp_funcs || !pp_funcs->display_configuration_changed) + if (!pp_funcs || !pp_funcs->display_configuration_changed + || !pp_funcs->display_clock_voltage_request) return; + request.clock_type = dc_to_pp_clock_type(DM_PP_CLOCK_TYPE_DCFCLK); + request.clock_freq_in_khz = req->hard_min_dcefclk_khz; + pp_funcs->display_clock_voltage_request(pp_handle, &request); + + request.clock_type = dc_to_pp_clock_type(DM_PP_CLOCK_TYPE_FCLK); + request.clock_freq_in_khz = req->hard_min_fclk_khz; + pp_funcs->display_clock_voltage_request(pp_handle, &request); + amdgpu_dpm_display_configuration_changed(adev); } -- 1.9.1
