On Thu, Jun 28, 2018 at 5:10 AM, rex zhu <rex.zhu at amd.com> wrote:
> From: Rex Zhu <Rex.Zhu at amd.com>
>
> Convert clock unit 10KHz to KHz as the data sturct defined.
> e.g.
> struct pp_clock_with_latency {
> uint32_t clocks_in_khz;
> uint32_t latency_in_us;
> };
> Meanwhile revert the same conversion in display side.
>
> Acked-by: Alex Deucher <alexander.deucher at amd.com>
> Acked-by: Harry Wentland <harry.wentland at amd.com>
> Signed-off-by: Rex Zhu <Rex.Zhu at amd.com>
Acked-by: Alex Deucher <alexander.deucher at amd.com>
> ---
> .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c | 18 +++++++-----------
> drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c | 4 ++--
> drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 10 +++++-----
> drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c | 16 ++++++++--------
> 4 files changed, 22 insertions(+), 26 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
> index cf92d7a..596d49d 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
> @@ -203,8 +203,7 @@ static void pp_to_dc_clock_levels(
>
> for (i = 0; i < dc_clks->num_levels; i++) {
> DRM_INFO("DM_PPLIB:\t %d\n", pp_clks->clock[i]);
> - /* translate 10kHz to kHz */
> - dc_clks->clocks_in_khz[i] = pp_clks->clock[i] * 10;
> + dc_clks->clocks_in_khz[i] = pp_clks->clock[i];
> }
> }
>
> @@ -229,9 +228,8 @@ static void pp_to_dc_clock_levels_with_latency(
> DC_DECODE_PP_CLOCK_TYPE(dc_clk_type));
>
> for (i = 0; i < clk_level_info->num_levels; i++) {
> - DRM_DEBUG("DM_PPLIB:\t %d in 10kHz\n", pp_clks->data[i].clocks_in_khz);
> - /* translate 10kHz to kHz */
> - clk_level_info->data[i].clocks_in_khz = pp_clks->data[i].clocks_in_khz * 10;
> + DRM_DEBUG("DM_PPLIB:\t %d in kHz\n", pp_clks->data[i].clocks_in_khz);
> + clk_level_info->data[i].clocks_in_khz = pp_clks->data[i].clocks_in_khz;
> clk_level_info->data[i].latency_in_us = pp_clks->data[i].latency_in_us;
> }
> }
> @@ -257,9 +255,8 @@ static void pp_to_dc_clock_levels_with_voltage(
> DC_DECODE_PP_CLOCK_TYPE(dc_clk_type));
>
> for (i = 0; i < clk_level_info->num_levels; i++) {
> - DRM_INFO("DM_PPLIB:\t %d in 10kHz\n", pp_clks->data[i].clocks_in_khz);
> - /* translate 10kHz to kHz */
> - clk_level_info->data[i].clocks_in_khz = pp_clks->data[i].clocks_in_khz * 10;
> + DRM_INFO("DM_PPLIB:\t %d in kHz\n", pp_clks->data[i].clocks_in_khz);
> + clk_level_info->data[i].clocks_in_khz = pp_clks->data[i].clocks_in_khz;
> clk_level_info->data[i].voltage_in_mv = pp_clks->data[i].voltage_in_mv;
> }
> }
> @@ -434,9 +431,8 @@ bool dm_pp_get_static_clocks(
> return false;
>
> static_clk_info->max_clocks_state = pp_clk_info.max_clocks_state;
> - /* translate 10kHz to kHz */
> - static_clk_info->max_mclk_khz = pp_clk_info.max_memory_clock * 10;
> - static_clk_info->max_sclk_khz = pp_clk_info.max_engine_clock * 10;
> + static_clk_info->max_mclk_khz = pp_clk_info.max_memory_clock;
> + static_clk_info->max_sclk_khz = pp_clk_info.max_engine_clock;
>
> return true;
> }
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
> index 0bbf11d..07cc98c 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
> @@ -993,7 +993,7 @@ static int smu10_get_clock_by_type_with_latency(struct pp_hwmgr *hwmgr,
>
> clocks->num_levels = 0;
> for (i = 0; i < pclk_vol_table->count; i++) {
> - clocks->data[i].clocks_in_khz = pclk_vol_table->entries[i].clk;
> + clocks->data[i].clocks_in_khz = pclk_vol_table->entries[i].clk * 10;
> clocks->data[i].latency_in_us = latency_required ?
> smu10_get_mem_latency(hwmgr,
> pclk_vol_table->entries[i].clk) :
> @@ -1044,7 +1044,7 @@ static int smu10_get_clock_by_type_with_voltage(struct pp_hwmgr *hwmgr,
>
> clocks->num_levels = 0;
> for (i = 0; i < pclk_vol_table->count; i++) {
> - clocks->data[i].clocks_in_khz = pclk_vol_table->entries[i].clk;
> + clocks->data[i].clocks_in_khz = pclk_vol_table->entries[i].clk * 10;
> clocks->data[i].voltage_in_mv = pclk_vol_table->entries[i].vol;
> clocks->num_levels++;
> }
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> index 0f240b2..3e54de0 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> @@ -4061,7 +4061,7 @@ static void vega10_get_sclks(struct pp_hwmgr *hwmgr,
> for (i = 0; i < dep_table->count; i++) {
> if (dep_table->entries[i].clk) {
> clocks->data[clocks->num_levels].clocks_in_khz =
> - dep_table->entries[i].clk;
> + dep_table->entries[i].clk * 10;
> clocks->num_levels++;
> }
> }
> @@ -4086,7 +4086,7 @@ static void vega10_get_memclocks(struct pp_hwmgr *hwmgr,
> clocks->data[clocks->num_levels].clocks_in_khz =
> data->mclk_latency_table.entries
> [data->mclk_latency_table.count].frequency =
> - dep_table->entries[i].clk;
> + dep_table->entries[i].clk * 10;
> clocks->data[clocks->num_levels].latency_in_us =
> data->mclk_latency_table.entries
> [data->mclk_latency_table.count].latency = 25;
> @@ -4106,7 +4106,7 @@ static void vega10_get_dcefclocks(struct pp_hwmgr *hwmgr,
> uint32_t i;
>
> for (i = 0; i < dep_table->count; i++) {
> - clocks->data[i].clocks_in_khz = dep_table->entries[i].clk;
> + clocks->data[i].clocks_in_khz = dep_table->entries[i].clk * 10;
> clocks->data[i].latency_in_us = 0;
> clocks->num_levels++;
> }
> @@ -4122,7 +4122,7 @@ static void vega10_get_socclocks(struct pp_hwmgr *hwmgr,
> uint32_t i;
>
> for (i = 0; i < dep_table->count; i++) {
> - clocks->data[i].clocks_in_khz = dep_table->entries[i].clk;
> + clocks->data[i].clocks_in_khz = dep_table->entries[i].clk * 10;
> clocks->data[i].latency_in_us = 0;
> clocks->num_levels++;
> }
> @@ -4182,7 +4182,7 @@ static int vega10_get_clock_by_type_with_voltage(struct pp_hwmgr *hwmgr,
> }
>
> for (i = 0; i < dep_table->count; i++) {
> - clocks->data[i].clocks_in_khz = dep_table->entries[i].clk;
> + clocks->data[i].clocks_in_khz = dep_table->entries[i].clk * 10;
> clocks->data[i].voltage_in_mv = (uint32_t)(table_info->vddc_lookup_table->
> entries[dep_table->entries[i].vddInd].us_vdd);
> clocks->num_levels++;
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
> index 782e209..ada4345 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
> @@ -1576,7 +1576,7 @@ static int vega12_get_sclks(struct pp_hwmgr *hwmgr,
>
> for (i = 0; i < ucount; i++) {
> clocks->data[i].clocks_in_khz =
> - dpm_table->dpm_levels[i].value * 100;
> + dpm_table->dpm_levels[i].value * 1000;
>
> clocks->data[i].latency_in_us = 0;
> }
> @@ -1608,7 +1608,7 @@ static int vega12_get_memclocks(struct pp_hwmgr *hwmgr,
>
> for (i = 0; i < ucount; i++) {
> clocks->data[i].clocks_in_khz =
> - dpm_table->dpm_levels[i].value * 100;
> + dpm_table->dpm_levels[i].value * 1000;
>
> clocks->data[i].latency_in_us =
> data->mclk_latency_table.entries[i].latency =
> @@ -1638,7 +1638,7 @@ static int vega12_get_dcefclocks(struct pp_hwmgr *hwmgr,
>
> for (i = 0; i < ucount; i++) {
> clocks->data[i].clocks_in_khz =
> - dpm_table->dpm_levels[i].value * 100;
> + dpm_table->dpm_levels[i].value * 1000;
>
> clocks->data[i].latency_in_us = 0;
> }
> @@ -1666,7 +1666,7 @@ static int vega12_get_socclocks(struct pp_hwmgr *hwmgr,
>
> for (i = 0; i < ucount; i++) {
> clocks->data[i].clocks_in_khz =
> - dpm_table->dpm_levels[i].value * 100;
> + dpm_table->dpm_levels[i].value * 1000;
>
> clocks->data[i].latency_in_us = 0;
> }
> @@ -1838,8 +1838,8 @@ static int vega12_print_clock_levels(struct pp_hwmgr *hwmgr,
> return -1);
> for (i = 0; i < clocks.num_levels; i++)
> size += sprintf(buf + size, "%d: %uMhz %s\n",
> - i, clocks.data[i].clocks_in_khz / 100,
> - (clocks.data[i].clocks_in_khz == now) ? "*" : "");
> + i, clocks.data[i].clocks_in_khz / 1000,
> + (clocks.data[i].clocks_in_khz / 1000 == now) ? "*" : "");
> break;
>
> case PP_MCLK:
> @@ -1854,8 +1854,8 @@ static int vega12_print_clock_levels(struct pp_hwmgr *hwmgr,
> return -1);
> for (i = 0; i < clocks.num_levels; i++)
> size += sprintf(buf + size, "%d: %uMhz %s\n",
> - i, clocks.data[i].clocks_in_khz / 100,
> - (clocks.data[i].clocks_in_khz == now) ? "*" : "");
> + i, clocks.data[i].clocks_in_khz / 1000,
> + (clocks.data[i].clocks_in_khz / 1000 == now) ? "*" : "");
> break;
>
> case PP_PCIE:
> --
> 1.9.1
>
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