rename clocks_in_khz to clocks_in_10khz
Just follow
commit 90f132cf443f ("drm/amd/display: Convert 10kHz clks from PPLib into kHz")
1. clock-unit in smu is 10KHz on legacy asics.
2. dal transfer the clock value read from
powerplay by *10. so change the variable name to avoid confuse.
Signed-off-by: Rex Zhu <Rex.Zhu at amd.com>
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c | 8 ++++----
drivers/gpu/drm/amd/include/dm_pp_interface.h | 4 ++--
drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c | 4 ++--
drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 10 +++++-----
drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c | 16 ++++++++--------
5 files changed, 21 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
index cf92d7a..43977db 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
@@ -229,9 +229,9 @@ static void pp_to_dc_clock_levels_with_latency(
DC_DECODE_PP_CLOCK_TYPE(dc_clk_type));
for (i = 0; i < clk_level_info->num_levels; i++) {
- DRM_DEBUG("DM_PPLIB:\t %d in 10kHz\n", pp_clks->data[i].clocks_in_khz);
+ DRM_DEBUG("DM_PPLIB:\t %d in 10kHz\n", pp_clks->data[i].clocks_in_10khz);
/* translate 10kHz to kHz */
- clk_level_info->data[i].clocks_in_khz = pp_clks->data[i].clocks_in_khz * 10;
+ clk_level_info->data[i].clocks_in_khz = pp_clks->data[i].clocks_in_10khz * 10;
clk_level_info->data[i].latency_in_us = pp_clks->data[i].latency_in_us;
}
}
@@ -257,9 +257,9 @@ static void pp_to_dc_clock_levels_with_voltage(
DC_DECODE_PP_CLOCK_TYPE(dc_clk_type));
for (i = 0; i < clk_level_info->num_levels; i++) {
- DRM_INFO("DM_PPLIB:\t %d in 10kHz\n", pp_clks->data[i].clocks_in_khz);
+ DRM_INFO("DM_PPLIB:\t %d in 10kHz\n", pp_clks->data[i].clocks_in_10khz);
/* translate 10kHz to kHz */
- clk_level_info->data[i].clocks_in_khz = pp_clks->data[i].clocks_in_khz * 10;
+ clk_level_info->data[i].clocks_in_khz = pp_clks->data[i].clocks_in_10khz * 10;
clk_level_info->data[i].voltage_in_mv = pp_clks->data[i].voltage_in_mv;
}
}
diff --git a/drivers/gpu/drm/amd/include/dm_pp_interface.h b/drivers/gpu/drm/amd/include/dm_pp_interface.h
index 7852952..0177491 100644
--- a/drivers/gpu/drm/amd/include/dm_pp_interface.h
+++ b/drivers/gpu/drm/amd/include/dm_pp_interface.h
@@ -165,7 +165,7 @@ struct amd_pp_clocks {
};
struct pp_clock_with_latency {
- uint32_t clocks_in_khz;
+ uint32_t clocks_in_10khz;
uint32_t latency_in_us;
};
@@ -175,7 +175,7 @@ struct pp_clock_levels_with_latency {
};
struct pp_clock_with_voltage {
- uint32_t clocks_in_khz;
+ uint32_t clocks_in_10khz;
uint32_t voltage_in_mv;
};
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
index d4bc83e..a2a394c 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
@@ -993,7 +993,7 @@ static int smu10_get_clock_by_type_with_latency(struct pp_hwmgr *hwmgr,
clocks->num_levels = 0;
for (i = 0; i < pclk_vol_table->count; i++) {
- clocks->data[i].clocks_in_khz = pclk_vol_table->entries[i].clk;
+ clocks->data[i].clocks_in_10khz = pclk_vol_table->entries[i].clk;
clocks->data[i].latency_in_us = latency_required ?
smu10_get_mem_latency(hwmgr,
pclk_vol_table->entries[i].clk) :
@@ -1044,7 +1044,7 @@ static int smu10_get_clock_by_type_with_voltage(struct pp_hwmgr *hwmgr,
clocks->num_levels = 0;
for (i = 0; i < pclk_vol_table->count; i++) {
- clocks->data[i].clocks_in_khz = pclk_vol_table->entries[i].clk;
+ clocks->data[i].clocks_in_10khz = pclk_vol_table->entries[i].clk;
clocks->data[i].voltage_in_mv = pclk_vol_table->entries[i].vol;
clocks->num_levels++;
}
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
index 3b8d36d..a739201 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
@@ -4066,7 +4066,7 @@ static void vega10_get_sclks(struct pp_hwmgr *hwmgr,
for (i = 0; i < dep_table->count; i++) {
if (dep_table->entries[i].clk) {
- clocks->data[clocks->num_levels].clocks_in_khz =
+ clocks->data[clocks->num_levels].clocks_in_10khz =
dep_table->entries[i].clk;
clocks->num_levels++;
}
@@ -4101,7 +4101,7 @@ static void vega10_get_memclocks(struct pp_hwmgr *hwmgr,
for (i = 0; i < dep_table->count; i++) {
if (dep_table->entries[i].clk) {
- clocks->data[clocks->num_levels].clocks_in_khz =
+ clocks->data[clocks->num_levels].clocks_in_10khz =
data->mclk_latency_table.entries
[data->mclk_latency_table.count].frequency =
dep_table->entries[i].clk;
@@ -4126,7 +4126,7 @@ static void vega10_get_dcefclocks(struct pp_hwmgr *hwmgr,
uint32_t i;
for (i = 0; i < dep_table->count; i++) {
- clocks->data[i].clocks_in_khz = dep_table->entries[i].clk;
+ clocks->data[i].clocks_in_10khz = dep_table->entries[i].clk;
clocks->data[i].latency_in_us = 0;
clocks->num_levels++;
}
@@ -4142,7 +4142,7 @@ static void vega10_get_socclocks(struct pp_hwmgr *hwmgr,
uint32_t i;
for (i = 0; i < dep_table->count; i++) {
- clocks->data[i].clocks_in_khz = dep_table->entries[i].clk;
+ clocks->data[i].clocks_in_10khz = dep_table->entries[i].clk;
clocks->data[i].latency_in_us = 0;
clocks->num_levels++;
}
@@ -4202,7 +4202,7 @@ static int vega10_get_clock_by_type_with_voltage(struct pp_hwmgr *hwmgr,
}
for (i = 0; i < dep_table->count; i++) {
- clocks->data[i].clocks_in_khz = dep_table->entries[i].clk;
+ clocks->data[i].clocks_in_10khz = dep_table->entries[i].clk;
clocks->data[i].voltage_in_mv = (uint32_t)(table_info->vddc_lookup_table->
entries[dep_table->entries[i].vddInd].us_vdd);
clocks->num_levels++;
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
index 782e209..7425049 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
@@ -1575,7 +1575,7 @@ static int vega12_get_sclks(struct pp_hwmgr *hwmgr,
VG12_PSUEDO_NUM_GFXCLK_DPM_LEVELS : dpm_table->count;
for (i = 0; i < ucount; i++) {
- clocks->data[i].clocks_in_khz =
+ clocks->data[i].clocks_in_10khz =
dpm_table->dpm_levels[i].value * 100;
clocks->data[i].latency_in_us = 0;
@@ -1607,7 +1607,7 @@ static int vega12_get_memclocks(struct pp_hwmgr *hwmgr,
VG12_PSUEDO_NUM_UCLK_DPM_LEVELS : dpm_table->count;
for (i = 0; i < ucount; i++) {
- clocks->data[i].clocks_in_khz =
+ clocks->data[i].clocks_in_10khz =
dpm_table->dpm_levels[i].value * 100;
clocks->data[i].latency_in_us =
@@ -1637,7 +1637,7 @@ static int vega12_get_dcefclocks(struct pp_hwmgr *hwmgr,
VG12_PSUEDO_NUM_DCEFCLK_DPM_LEVELS : dpm_table->count;
for (i = 0; i < ucount; i++) {
- clocks->data[i].clocks_in_khz =
+ clocks->data[i].clocks_in_10khz =
dpm_table->dpm_levels[i].value * 100;
clocks->data[i].latency_in_us = 0;
@@ -1665,7 +1665,7 @@ static int vega12_get_socclocks(struct pp_hwmgr *hwmgr,
VG12_PSUEDO_NUM_SOCCLK_DPM_LEVELS : dpm_table->count;
for (i = 0; i < ucount; i++) {
- clocks->data[i].clocks_in_khz =
+ clocks->data[i].clocks_in_10khz =
dpm_table->dpm_levels[i].value * 100;
clocks->data[i].latency_in_us = 0;
@@ -1838,8 +1838,8 @@ static int vega12_print_clock_levels(struct pp_hwmgr *hwmgr,
return -1);
for (i = 0; i < clocks.num_levels; i++)
size += sprintf(buf + size, "%d: %uMhz %s\n",
- i, clocks.data[i].clocks_in_khz / 100,
- (clocks.data[i].clocks_in_khz == now) ? "*" : "");
+ i, clocks.data[i].clocks_in_10khz / 100,
+ (clocks.data[i].clocks_in_10khz == now) ? "*" : "");
break;
case PP_MCLK:
@@ -1854,8 +1854,8 @@ static int vega12_print_clock_levels(struct pp_hwmgr *hwmgr,
return -1);
for (i = 0; i < clocks.num_levels; i++)
size += sprintf(buf + size, "%d: %uMhz %s\n",
- i, clocks.data[i].clocks_in_khz / 100,
- (clocks.data[i].clocks_in_khz == now) ? "*" : "");
+ i, clocks.data[i].clocks_in_10khz / 100,
+ (clocks.data[i].clocks_in_10khz == now) ? "*" : "");
break;
case PP_PCIE:
--
1.9.1
