On 6/8/2018 1:08 PM, Christian König wrote:
> Am 08.06.2018 um 07:23 schrieb zhoucm1:
>>
>>
>> On 2018å¹´06æ??08æ?¥ 12:54, Shirish S wrote:
>>> This patch is extends the usage of WB in
>>> gfx8's ib test which was originally
>>> implemented in the below upstream patch:
>>> "ed9324a drm/amdgpu: change gfx9 ib test to use WB"
>
> You could copy the commit message from ed9324a to better explain why
> we do it, but that is only nice to have.
>
>>>
>>> Signed-off-by: Shirish S <shirish.s at amd.com>
>> Reviewed-by: Chunming Zhou <david1.zhou at amd.com>
>
> Reviewed-by: Christian König <christian.koenig at amd.com>
>
Thanks Christian & david, shall re-send with the updated commit message
and RB's.
Regards,
Shirish S
>>
>>> ---
>>> Â drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 35
>>> +++++++++++++++++++++--------------
>>> Â 1 file changed, 21 insertions(+), 14 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
>>> b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
>>> index 818874b..61452c7 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
>>> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
>>> @@ -866,26 +866,32 @@ static int gfx_v8_0_ring_test_ib(struct
>>> amdgpu_ring *ring, long timeout)
>>> Â Â Â Â Â struct amdgpu_device *adev = ring->adev;
>>> Â Â Â Â Â struct amdgpu_ib ib;
>>> Â Â Â Â Â struct dma_fence *f = NULL;
>>> -Â Â Â uint32_t scratch;
>>> -Â Â Â uint32_t tmp = 0;
>>> +
>>> +Â Â Â unsigned int index;
>>> +Â Â Â uint64_t gpu_addr;
>>> +Â Â Â uint32_t tmp;
>>> Â Â Â Â Â long r;
>>> Â -Â Â Â r = amdgpu_gfx_scratch_get(adev, &scratch);
>>> +Â Â Â r = amdgpu_device_wb_get(adev, &index);
>>> Â Â Â Â Â if (r) {
>>> -Â Â Â Â Â Â Â DRM_ERROR("amdgpu: failed to get scratch reg (%ld).\n", r);
>>> +Â Â Â Â Â Â Â dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r);
>>> Â Â Â Â Â Â Â Â Â return r;
>>> Â Â Â Â Â }
>>> -Â Â Â WREG32(scratch, 0xCAFEDEAD);
>>> +
>>> +Â Â Â gpu_addr = adev->wb.gpu_addr + (index * 4);
>>> +Â Â Â adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD);
>>> Â Â Â Â Â memset(&ib, 0, sizeof(ib));
>>> -Â Â Â r = amdgpu_ib_get(adev, NULL, 256, &ib);
>>> +Â Â Â r = amdgpu_ib_get(adev, NULL, 16, &ib);
>>> Â Â Â Â Â if (r) {
>>> Â Â Â Â Â Â Â Â Â DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
>>> Â Â Â Â Â Â Â Â Â goto err1;
>>> Â Â Â Â Â }
>>> -Â Â Â ib.ptr[0] = PACKET3(PACKET3_SET_UCONFIG_REG, 1);
>>> -Â Â Â ib.ptr[1] = ((scratch - PACKET3_SET_UCONFIG_REG_START));
>>> -Â Â Â ib.ptr[2] = 0xDEADBEEF;
>>> -Â Â Â ib.length_dw = 3;
>>> +Â Â Â ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3);
>>> +Â Â Â ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM;
>>> +Â Â Â ib.ptr[2] = lower_32_bits(gpu_addr);
>>> +Â Â Â ib.ptr[3] = upper_32_bits(gpu_addr);
>>> +Â Â Â ib.ptr[4] = 0xDEADBEEF;
>>> +Â Â Â ib.length_dw = 5;
>>> Â Â Â Â Â Â r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
>>> Â Â Â Â Â if (r)
>>> @@ -900,20 +906,21 @@ static int gfx_v8_0_ring_test_ib(struct
>>> amdgpu_ring *ring, long timeout)
>>> Â Â Â Â Â Â Â Â Â DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
>>> Â Â Â Â Â Â Â Â Â goto err2;
>>> Â Â Â Â Â }
>>> -Â Â Â tmp = RREG32(scratch);
>>> +
>>> +Â Â Â tmp = adev->wb.wb[index];
>>> Â Â Â Â Â if (tmp == 0xDEADBEEF) {
>>> Â Â Â Â Â Â Â Â Â DRM_DEBUG("ib test on ring %d succeeded\n", ring->idx);
>>> Â Â Â Â Â Â Â Â Â r = 0;
>>> Â Â Â Â Â } else {
>>> -Â Â Â Â Â Â Â DRM_ERROR("amdgpu: ib test failed (scratch(0x%04X)=0x%08X)\n",
>>> -Â Â Â Â Â Â Â Â Â Â Â Â Â scratch, tmp);
>>> +Â Â Â Â Â Â Â DRM_ERROR("ib test on ring %d failed\n", ring->idx);
>>> Â Â Â Â Â Â Â Â Â r = -EINVAL;
>>> Â Â Â Â Â }
>>> +
>>> Â err2:
>>> Â Â Â Â Â amdgpu_ib_free(adev, &ib, NULL);
>>> Â Â Â Â Â dma_fence_put(f);
>>> Â err1:
>>> -Â Â Â amdgpu_gfx_scratch_free(adev, scratch);
>>> +Â Â Â amdgpu_device_wb_free(adev, index);
>>> Â Â Â Â Â return r;
>>> Â }
>>
>> _______________________________________________
>> amd-gfx mailing list
>> amd-gfx at lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
>
--
Regards,
Shirish S
