The patch possibly cause ASIC hung during S3. GFXOFF should be disabled as the first step when suspend, and then enabled again as the last step when resume. Otherwise, any mmio access will result to aisc hung.
Regards,
Hawking
-----Original Message-----
From: amd-gfx <amd-gfx-bounces@xxxxxxxxxxxxxxxxxxxxx> On Behalf Of Rex Zhu
Sent: 2018å¹´6æ??5æ?¥ 16:25
To: amd-gfx at lists.freedesktop.org
Cc: Zhu, Rex <Rex.Zhu at amd.com>
Subject: [PATCH v2 2/2] drm/amdgpu: Make gfx_off control by GFX ip
v2: Delete the dead gfx off code in ip_suspend.
gfx off should be controlled by GFX IP.
Powerplay only export interface to gfx ip.
This logic is same as uvd/vce cg/pg.
Signed-off-by: Rex Zhu <Rex.Zhu at amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 6 ------
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 4 ++++
drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c | 4 ++--
3 files changed, 6 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 4003038..5fb281c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1940,12 +1940,6 @@ int amdgpu_device_ip_suspend(struct amdgpu_device *adev)
if (amdgpu_sriov_vf(adev))
amdgpu_virt_request_full_gpu(adev, false);
- /* ungate SMC block powergating */
- if (adev->powerplay.pp_feature & PP_GFXOFF_MASK)
- amdgpu_device_ip_set_powergating_state(adev,
- AMD_IP_BLOCK_TYPE_SMC,
- AMD_CG_STATE_UNGATE);
-
/* ungate SMC block first */
r = amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_SMC,
AMD_CG_STATE_UNGATE);
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index c382969..86c5f7e 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -3712,6 +3712,10 @@ static int gfx_v9_0_set_powergating_state(void *handle,
/* update mgcg state */
gfx_v9_0_update_gfx_mg_power_gating(adev, enable);
+
+ /* update gfx off through smu */
+ if (adev->powerplay.pp_funcs->set_powergating_by_smu)
+ amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_GFX,
+enable);
break;
default:
break;
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
index b9e6dfb..5abae28 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
@@ -314,7 +314,7 @@ static int smu10_disable_gfx_off(struct pp_hwmgr *hwmgr)
static int smu10_disable_dpm_tasks(struct pp_hwmgr *hwmgr) {
- return smu10_disable_gfx_off(hwmgr);
+ return 0;
}
static int smu10_enable_gfx_off(struct pp_hwmgr *hwmgr) @@ -329,7 +329,7 @@ static int smu10_enable_gfx_off(struct pp_hwmgr *hwmgr)
static int smu10_enable_dpm_tasks(struct pp_hwmgr *hwmgr) {
- return smu10_enable_gfx_off(hwmgr);
+ return 0;
}
static int smu10_gfx_off_control(struct pp_hwmgr *hwmgr, bool enable)
--
1.9.1
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