On 2018-05-27 09:46 PM, Quan, Evan wrote:
>> +Â Â Â Â Â Â Â Â Â Â Â Â Â Â /* translate 10kHz to kHz */
>> +Â Â Â Â Â Â Â Â Â Â Â Â Â Â clk_level_info->data[i].clocks_in_khz = pp_clks->data[i].clocks_in_khz;
>> +Â Â Â Â Â Â Â Â Â Â Â Â Â Â clk_level_info->data[i].latency_in_us = pp_clks->data[i].clocks_in_khz;
>
> This seems a typo(latency_in_us = clocks_in_khz ?).
>
Definitely a typo. Thanks for spotting this.
> And the comment does not meet the code. If it translates 10kHz to kHz, why there is no "*10"?
>> +Â Â Â Â Â Â }
>
I'll send a patch with fixes for both. No need for the comment here, just left-over from copy-paste.
Harry
>
> Regards,
>
> Evan
>
> ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
> *From:* amd-gfx <amd-gfx-bounces at lists.freedesktop.org> on behalf of Alex Deucher <alexdeucher at gmail.com>
> *Sent:* Thursday, May 24, 2018 12:35:52 PM
> *To:* Wentland, Harry
> *Cc:* Cheng, Tony; Lipski, Mikita; Zhu, Rex; Wu, Hersen; amd-gfx list
> *Subject:* Re: [PATCH] drm/amd/display: Implement dm_pp_get_clock_levels_by_type_with_latency
> Â
> On Wed, May 23, 2018 at 1:51 PM, Harry Wentland <harry.wentland at amd.com> wrote:
>> This is required so we use the correct minimum clocks for Vega. Without
>> this pplib will never be able to enter the lowest clock states.
>>
>> Signed-off-by: Harry Wentland <harry.wentland at amd.com>
>> ---
>> .../display/amdgpu_dm/amdgpu_dm_services.c   | 46 ++++++++++++++++++-
>>Â 1 file changed, 44 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c
>> index 0229c7edb8ad..30ddd329104d 100644
>> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c
>> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c
>> @@ -234,6 +234,34 @@ static void pp_to_dc_clock_levels(
>>Â Â Â Â Â Â Â Â }
>>Â }
>>
>> +static void pp_to_dc_clock_levels_with_latency(
>> +Â Â Â Â Â Â Â Â Â Â Â Â Â Â const struct pp_clock_levels_with_latency *pp_clks,
>> +Â Â Â Â Â Â Â Â Â Â Â Â Â Â struct dm_pp_clock_levels_with_latency *clk_level_info,
>> +Â Â Â Â Â Â Â Â Â Â Â Â Â Â enum dm_pp_clock_type dc_clk_type)
>> +{
>> +Â Â Â Â Â Â uint32_t i;
>> +
>> +Â Â Â Â Â Â if (pp_clks->num_levels > DM_PP_MAX_CLOCK_LEVELS) {
>> +Â Â Â Â Â Â Â Â Â Â Â Â Â Â DRM_INFO("DM_PPLIB: Warning: %s clock: number of levels %d exceeds maximum of %d!\n",
>> +Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â DC_DECODE_PP_CLOCK_TYPE(dc_clk_type),
>> +Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â pp_clks->num_levels,
>> +Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â DM_PP_MAX_CLOCK_LEVELS);
>> +
>> +Â Â Â Â Â Â Â Â Â Â Â Â Â Â clk_level_info->num_levels = DM_PP_MAX_CLOCK_LEVELS;
>> +Â Â Â Â Â Â } else
>> +Â Â Â Â Â Â Â Â Â Â Â Â Â Â clk_level_info->num_levels = pp_clks->num_levels;
>> +
>> +Â Â Â Â Â Â DRM_INFO("DM_PPLIB: values for %s clock\n",
>> +Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â DC_DECODE_PP_CLOCK_TYPE(dc_clk_type));
>> +
>> +Â Â Â Â Â Â for (i = 0; i < clk_level_info->num_levels; i++) {
>> +Â Â Â Â Â Â Â Â Â Â Â Â Â Â DRM_INFO("DM_PPLIB:\t %d\n", pp_clks->data[i].clocks_in_khz);
>
> leftover debugging output? Maybe make that DRM_DEBUG? With that addressed:
> Acked-by: Alex Deucher <alexander.deucher at amd.com>
>
> Alex
>
>> +Â Â Â Â Â Â Â Â Â Â Â Â Â Â /* translate 10kHz to kHz */
>> +Â Â Â Â Â Â Â Â Â Â Â Â Â Â clk_level_info->data[i].clocks_in_khz = pp_clks->data[i].clocks_in_khz;
>> +Â Â Â Â Â Â Â Â Â Â Â Â Â Â clk_level_info->data[i].latency_in_us = pp_clks->data[i].clocks_in_khz;
>> +Â Â Â Â Â Â }
>> +}
>> +
>>Â bool dm_pp_get_clock_levels_by_type(
>>Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â const struct dc_context *ctx,
>>Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â enum dm_pp_clock_type clk_type,
>> @@ -311,8 +339,22 @@ bool dm_pp_get_clock_levels_by_type_with_latency(
>>Â Â Â Â Â Â Â Â enum dm_pp_clock_type clk_type,
>>Â Â Â Â Â Â Â Â struct dm_pp_clock_levels_with_latency *clk_level_info)
>>Â {
>> -Â Â Â Â Â Â /* TODO: to be implemented */
>> -Â Â Â Â Â Â return false;
>> +Â Â Â Â Â Â struct amdgpu_device *adev = ctx->driver_context;
>> +Â Â Â Â Â Â void *pp_handle = adev->powerplay.pp_handle;
>> +Â Â Â Â Â Â struct pp_clock_levels_with_latency pp_clks = { 0 };
>> +Â Â Â Â Â Â const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
>> +
>> +Â Â Â Â Â Â if (!pp_funcs->get_clock_by_type_with_latency)
>> +Â Â Â Â Â Â Â Â Â Â Â Â Â Â return false;
>> +
>> +Â Â Â Â Â Â if (pp_funcs->get_clock_by_type_with_latency(pp_handle,
>> +Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â dc_to_pp_clock_type(clk_type),
>> +Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â &pp_clks))
>> +Â Â Â Â Â Â Â Â Â Â Â Â Â Â return false;
>> +
>> +Â Â Â Â Â Â pp_to_dc_clock_levels_with_latency(&pp_clks, clk_level_info, clk_type);
>> +
>> +Â Â Â Â Â Â return true;
>>Â }
>>
>>Â bool dm_pp_get_clock_levels_by_type_with_voltage(
>> --
>> 2.17.0
>>
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