From: Boyuan Zhang <boyuan.zhang@xxxxxxx>
Implement a patch to maunally reset read pointer
Signed-off-by: Boyuan Zhang <boyuan.zhang at amd.com>
---
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 43 +++++++++++++++++++++++++++++++++++
1 file changed, 43 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
index 34699f8..dcd1a9a 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
@@ -41,6 +41,7 @@ static void vcn_v1_0_set_dec_ring_funcs(struct amdgpu_device *adev);
static void vcn_v1_0_set_enc_ring_funcs(struct amdgpu_device *adev);
static void vcn_v1_0_set_jpeg_ring_funcs(struct amdgpu_device *adev);
static void vcn_v1_0_set_irq_funcs(struct amdgpu_device *adev);
+static void vcn_v1_0_jpeg_ring_set_patch_ring(struct amdgpu_ring *ring);
/**
* vcn_v1_0_early_init - set function pointers
@@ -1339,6 +1340,48 @@ static void vcn_v1_0_jpeg_ring_nop(struct amdgpu_ring *ring, uint32_t count)
}
}
+static void vcn_v1_0_jpeg_ring_set_patch_ring(struct amdgpu_ring *ring)
+{
+ struct amdgpu_device *adev = ring->adev;
+
+ uint32_t reg, val, mask, i;
+
+ reg = SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW);
+ val = lower_32_bits(ring->gpu_addr);
+ vcn_v1_0_jpeg_ring_emit_wreg(ring, reg, val);
+
+ reg = SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH);
+ val = upper_32_bits(ring->gpu_addr);
+ vcn_v1_0_jpeg_ring_emit_wreg(ring, reg, val);
+
+ for (i = 0; i <= 2; i++)
+ vcn_v1_0_jpeg_ring_mem_read(ring);
+
+ reg = SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_CNTL);
+ val = 0x13;
+ vcn_v1_0_jpeg_ring_emit_wreg(ring, reg, val);
+
+ reg = SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_REF_DATA);
+ val = 0x1;
+ vcn_v1_0_jpeg_ring_emit_wreg(ring, reg, val);
+
+ reg = SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_CNTL);
+ val = 0x1;
+ mask = 0x1;
+ vcn_v1_0_jpeg_ring_emit_reg_wait(ring, reg, val, mask);
+
+ for (i = 0; i <= 12; i++)
+ vcn_v1_0_jpeg_ring_nop(ring, 2);
+
+ reg = SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_RPTR);
+ val = 0;
+ vcn_v1_0_jpeg_ring_emit_wreg(ring, reg, val);
+
+ reg = SOC15_REG_OFFSET(UVD, 0, mmUVD_JRBC_RB_CNTL);
+ val = 0x12;
+ vcn_v1_0_jpeg_ring_emit_wreg(ring, reg, val);
+}
+
static int vcn_v1_0_set_interrupt_state(struct amdgpu_device *adev,
struct amdgpu_irq_src *source,
unsigned type,
--
2.7.4
