On Mon, Apr 23, 2018 at 7:41 AM, Nicolai Hähnle <nhaehnle at gmail.com> wrote: > From: Nicolai Hähnle <nicolai.haehnle at amd.com> > > Otherwise, the SQ may skip some of the register writes, or shader waves may > be allocated where we don't expect them, so that as a result we don't actually > reset all of the register SRAMs. This can lead to spurious ECC errors later on > if a shader uses an uninitialized register. > > Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=198883 > Signed-off-by: Nicolai Hähnle <nicolai.haehnle at amd.com> Should probably CC stable as well. Reviewed-by: Alex Deucher <alexander.deucher at amd.com> > --- > drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 7 +++++-- > 1 file changed, 5 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c > index a2d77bcf9a78..bdce864ab8fe 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c > @@ -1452,64 +1452,67 @@ static const u32 sgpr_init_compute_shader[] = > 0xbee60004, 0xbee70005, > 0xbeea0006, 0xbeeb0007, > 0xbee80008, 0xbee90009, > 0xbefc0000, 0xbf8a0000, > 0xbf810000, 0x00000000, > }; > > static const u32 vgpr_init_regs[] = > { > mmCOMPUTE_STATIC_THREAD_MGMT_SE0, 0xffffffff, > - mmCOMPUTE_RESOURCE_LIMITS, 0, > + mmCOMPUTE_RESOURCE_LIMITS, 0x1000000, /* CU_GROUP_COUNT=1 */ > mmCOMPUTE_NUM_THREAD_X, 256*4, > mmCOMPUTE_NUM_THREAD_Y, 1, > mmCOMPUTE_NUM_THREAD_Z, 1, > + mmCOMPUTE_PGM_RSRC1, 0x100004f, /* VGPRS=15 (64 logical VGPRs), SGPRS=1 (16 SGPRs), BULKY=1 */ > mmCOMPUTE_PGM_RSRC2, 20, > mmCOMPUTE_USER_DATA_0, 0xedcedc00, > mmCOMPUTE_USER_DATA_1, 0xedcedc01, > mmCOMPUTE_USER_DATA_2, 0xedcedc02, > mmCOMPUTE_USER_DATA_3, 0xedcedc03, > mmCOMPUTE_USER_DATA_4, 0xedcedc04, > mmCOMPUTE_USER_DATA_5, 0xedcedc05, > mmCOMPUTE_USER_DATA_6, 0xedcedc06, > mmCOMPUTE_USER_DATA_7, 0xedcedc07, > mmCOMPUTE_USER_DATA_8, 0xedcedc08, > mmCOMPUTE_USER_DATA_9, 0xedcedc09, > }; > > static const u32 sgpr1_init_regs[] = > { > mmCOMPUTE_STATIC_THREAD_MGMT_SE0, 0x0f, > - mmCOMPUTE_RESOURCE_LIMITS, 0x1000000, > + mmCOMPUTE_RESOURCE_LIMITS, 0x1000000, /* CU_GROUP_COUNT=1 */ > mmCOMPUTE_NUM_THREAD_X, 256*5, > mmCOMPUTE_NUM_THREAD_Y, 1, > mmCOMPUTE_NUM_THREAD_Z, 1, > + mmCOMPUTE_PGM_RSRC1, 0x240, /* SGPRS=9 (80 GPRS) */ > mmCOMPUTE_PGM_RSRC2, 20, > mmCOMPUTE_USER_DATA_0, 0xedcedc00, > mmCOMPUTE_USER_DATA_1, 0xedcedc01, > mmCOMPUTE_USER_DATA_2, 0xedcedc02, > mmCOMPUTE_USER_DATA_3, 0xedcedc03, > mmCOMPUTE_USER_DATA_4, 0xedcedc04, > mmCOMPUTE_USER_DATA_5, 0xedcedc05, > mmCOMPUTE_USER_DATA_6, 0xedcedc06, > mmCOMPUTE_USER_DATA_7, 0xedcedc07, > mmCOMPUTE_USER_DATA_8, 0xedcedc08, > mmCOMPUTE_USER_DATA_9, 0xedcedc09, > }; > > static const u32 sgpr2_init_regs[] = > { > mmCOMPUTE_STATIC_THREAD_MGMT_SE0, 0xf0, > mmCOMPUTE_RESOURCE_LIMITS, 0x1000000, > mmCOMPUTE_NUM_THREAD_X, 256*5, > mmCOMPUTE_NUM_THREAD_Y, 1, > mmCOMPUTE_NUM_THREAD_Z, 1, > + mmCOMPUTE_PGM_RSRC1, 0x240, /* SGPRS=9 (80 GPRS) */ > mmCOMPUTE_PGM_RSRC2, 20, > mmCOMPUTE_USER_DATA_0, 0xedcedc00, > mmCOMPUTE_USER_DATA_1, 0xedcedc01, > mmCOMPUTE_USER_DATA_2, 0xedcedc02, > mmCOMPUTE_USER_DATA_3, 0xedcedc03, > mmCOMPUTE_USER_DATA_4, 0xedcedc04, > mmCOMPUTE_USER_DATA_5, 0xedcedc05, > mmCOMPUTE_USER_DATA_6, 0xedcedc06, > mmCOMPUTE_USER_DATA_7, 0xedcedc07, > mmCOMPUTE_USER_DATA_8, 0xedcedc08, > -- > 2.14.1 > > _______________________________________________ > amd-gfx mailing list > amd-gfx at lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx
