[PATCH 4/6] drm/amdgpu/pm: document pp_dpm_sclk pp_dpm_mclk pp_dpm_pcie

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On Fri, Apr 20, 2018 at 2:16 AM, Zhu, Rex <Rex.Zhu at amd.com> wrote:
> Hi Alex,
>
>>  There  will be a '*' next to the level that is currently active.
>
> We need to add a level for deep sleep state.
> Otherwise, On Vega/Rv, when gpu in deepsleep, we can't set "*" for the current level.

I dropped that sentence for now.  We can revisit it later.  Thanks!

Alex

>
>
> Best Regards
> Rex
>
> -----Original Message-----
> From: amd-gfx [mailto:amd-gfx-bounces at lists.freedesktop.org] On Behalf Of Alex Deucher
> Sent: Friday, April 20, 2018 4:05 AM
> To: amd-gfx at lists.freedesktop.org
> Cc: Deucher, Alexander
> Subject: [PATCH 4/6] drm/amdgpu/pm: document pp_dpm_sclk pp_dpm_mclk pp_dpm_pcie
>
> Used for manually masking dpm states.
>
> Signed-off-by: Alex Deucher <alexander.deucher at amd.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 18 ++++++++++++++++++
>  1 file changed, 18 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> index 9982f1b1f8c4..3f1715b1a547 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> @@ -539,6 +539,24 @@ static ssize_t amdgpu_get_pp_od_clk_voltage(struct device *dev,
>
>  }
>
> +/**
> + * DOC: pp_dpm_sclk pp_dpm_mclk pp_dpm_pcie
> + *
> + * The amdgpu driver provides a sysfs API for adjusting what power levels
> + * are enabled for a given power state.  The files pp_dpm_sclk, pp_dpm_mclk,
> + * and pp_dpm_pcie are used for this.
> + *
> + * Reading back the files will show you the available power levels within
> + * the power state and the clock information for those levels.  There
> + * will be a '*' next to the level that is currently active.
> + *
> + * To manually adjust these states, first select manual using
> + * power_dpm_force_performance_level.  Writing a string of the level
> + * numbers to the file will select which levels you want to enable.
> + * E.g., writing 456 to the file will enable levels 4, 5, and 6.
> + *
> + */
> +
>  static ssize_t amdgpu_get_pp_dpm_sclk(struct device *dev,
>                 struct device_attribute *attr,
>                 char *buf)
> --
> 2.13.6
>
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