[PATCH] drm/amd/pp: Fix output erroneous clock info on RV

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On Thu, Apr 19, 2018 at 8:06 AM, Rex Zhu <Rex.Zhu at amd.com> wrote:
> Signed-off-by: Rex Zhu <Rex.Zhu at amd.com>

Please add a proper patch description explaining the change in units
and the switch to using dynamic state rather than hardcoded values.

> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c            |  4 +--
>  drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c | 42 ++++++++++++-----------
>  drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.h |  2 --
>  3 files changed, 24 insertions(+), 24 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> index 8f968bc..435fae9 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> @@ -1769,9 +1769,9 @@ static int amdgpu_debugfs_pm_info_pp(struct seq_file *m, struct amdgpu_device *a
>         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_SCLK, (void *)&value, &size))
>                 seq_printf(m, "\t%u MHz (SCLK)\n", value/100);
>         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK, (void *)&value, &size))
> -               seq_printf(m, "\t%u MHz (PSTATE_SCLK)\n", value/100);
> +               seq_printf(m, "\t%u MHz (PSTATE_SCLK)\n", value);
>         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK, (void *)&value, &size))
> -               seq_printf(m, "\t%u MHz (PSTATE_MCLK)\n", value/100);
> +               seq_printf(m, "\t%u MHz (PSTATE_MCLK)\n", value);
>         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDGFX, (void *)&value, &size))
>                 seq_printf(m, "\t%u mV (VDDGFX)\n", value);
>         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDNB, (void *)&value, &size))
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
> index 0f25226..f7bf5d5 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
> @@ -340,7 +340,7 @@ static int smu10_get_clock_voltage_dependency_table(struct pp_hwmgr *hwmgr,
>
>  static int smu10_populate_clock_table(struct pp_hwmgr *hwmgr)
>  {
> -       int result;
> +       uint32_t result;
>
>         struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
>         DpmClocks_t  *table = &(smu10_data->clock_table);
> @@ -386,11 +386,11 @@ static int smu10_populate_clock_table(struct pp_hwmgr *hwmgr)
>
>         smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMinGfxclkFrequency);
>         result = smum_get_argument(hwmgr);
> -       smu10_data->gfx_min_freq_limit = result * 100;
> +       smu10_data->gfx_min_freq_limit = result / 10 * 1000;
>
>         smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxGfxclkFrequency);
>         result = smum_get_argument(hwmgr);
> -       smu10_data->gfx_max_freq_limit = result * 100;
> +       smu10_data->gfx_max_freq_limit = result / 10 * 1000;
>

Are these changes just for rounding reasons?

>         return 0;
>  }
> @@ -472,6 +472,8 @@ static int smu10_hwmgr_backend_fini(struct pp_hwmgr *hwmgr)
>  static int smu10_dpm_force_dpm_level(struct pp_hwmgr *hwmgr,
>                                 enum amd_dpm_forced_level level)
>  {
> +       struct smu10_hwmgr *data = hwmgr->backend;
> +
>         if (hwmgr->smu_version < 0x1E3700) {
>                 pr_info("smu firmware version too old, can not set dpm level\n");
>                 return 0;
> @@ -482,7 +484,7 @@ static int smu10_dpm_force_dpm_level(struct pp_hwmgr *hwmgr,
>         case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
>                 smum_send_msg_to_smc_with_parameter(hwmgr,
>                                                 PPSMC_MSG_SetHardMinGfxClk,
> -                                               SMU10_UMD_PSTATE_PEAK_GFXCLK);
> +                                               data->gfx_max_freq_limit/100);
>                 smum_send_msg_to_smc_with_parameter(hwmgr,
>                                                 PPSMC_MSG_SetHardMinFclkByFreq,
>                                                 SMU10_UMD_PSTATE_PEAK_FCLK);
> @@ -495,7 +497,7 @@ static int smu10_dpm_force_dpm_level(struct pp_hwmgr *hwmgr,
>
>                 smum_send_msg_to_smc_with_parameter(hwmgr,
>                                                 PPSMC_MSG_SetSoftMaxGfxClk,
> -                                               SMU10_UMD_PSTATE_PEAK_GFXCLK);
> +                                               data->gfx_max_freq_limit/100);
>                 smum_send_msg_to_smc_with_parameter(hwmgr,
>                                                 PPSMC_MSG_SetSoftMaxFclkByFreq,
>                                                 SMU10_UMD_PSTATE_PEAK_FCLK);
> @@ -509,10 +511,10 @@ static int smu10_dpm_force_dpm_level(struct pp_hwmgr *hwmgr,
>         case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
>                 smum_send_msg_to_smc_with_parameter(hwmgr,
>                                                 PPSMC_MSG_SetHardMinGfxClk,
> -                                               SMU10_UMD_PSTATE_MIN_GFXCLK);
> +                                               data->gfx_min_freq_limit/100);
>                 smum_send_msg_to_smc_with_parameter(hwmgr,
>                                                 PPSMC_MSG_SetSoftMaxGfxClk,
> -                                               SMU10_UMD_PSTATE_MIN_GFXCLK);
> +                                               data->gfx_min_freq_limit/100);
>                 break;
>         case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
>                 smum_send_msg_to_smc_with_parameter(hwmgr,
> @@ -552,7 +554,7 @@ static int smu10_dpm_force_dpm_level(struct pp_hwmgr *hwmgr,
>         case AMD_DPM_FORCED_LEVEL_AUTO:
>                 smum_send_msg_to_smc_with_parameter(hwmgr,
>                                                 PPSMC_MSG_SetHardMinGfxClk,
> -                                               SMU10_UMD_PSTATE_MIN_GFXCLK);
> +                                               data->gfx_min_freq_limit/100);
>                 smum_send_msg_to_smc_with_parameter(hwmgr,
>                                                 PPSMC_MSG_SetHardMinFclkByFreq,
>                                                 SMU10_UMD_PSTATE_MIN_FCLK);
> @@ -565,7 +567,7 @@ static int smu10_dpm_force_dpm_level(struct pp_hwmgr *hwmgr,
>
>                 smum_send_msg_to_smc_with_parameter(hwmgr,
>                                                 PPSMC_MSG_SetSoftMaxGfxClk,
> -                                               SMU10_UMD_PSTATE_PEAK_GFXCLK);
> +                                               data->gfx_max_freq_limit/100);
>                 smum_send_msg_to_smc_with_parameter(hwmgr,
>                                                 PPSMC_MSG_SetSoftMaxFclkByFreq,
>                                                 SMU10_UMD_PSTATE_PEAK_FCLK);
> @@ -579,10 +581,10 @@ static int smu10_dpm_force_dpm_level(struct pp_hwmgr *hwmgr,
>         case AMD_DPM_FORCED_LEVEL_LOW:
>                 smum_send_msg_to_smc_with_parameter(hwmgr,
>                                                 PPSMC_MSG_SetHardMinGfxClk,
> -                                               SMU10_UMD_PSTATE_MIN_GFXCLK);
> +                                               data->gfx_min_freq_limit/100);
>                 smum_send_msg_to_smc_with_parameter(hwmgr,
>                                                 PPSMC_MSG_SetSoftMaxGfxClk,
> -                                               SMU10_UMD_PSTATE_MIN_GFXCLK);
> +                                               data->gfx_min_freq_limit/100);
>                 smum_send_msg_to_smc_with_parameter(hwmgr,
>                                                 PPSMC_MSG_SetHardMinFclkByFreq,
>                                                 SMU10_UMD_PSTATE_MIN_FCLK);
> @@ -730,21 +732,21 @@ static int smu10_print_clock_levels(struct pp_hwmgr *hwmgr,
>         struct smu10_hwmgr *data = (struct smu10_hwmgr *)(hwmgr->backend);
>         struct smu10_voltage_dependency_table *mclk_table =
>                         data->clock_vol_info.vdd_dep_on_fclk;
> -       int i, now, size = 0;
> +       uint32_t i, now, size = 0;
>
>         switch (type) {
>         case PP_SCLK:
> -               smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetGfxclkFrequency);
> +               smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetGfxclkFrequency, 0);

Is this change intended?  This looks like a separate bug fix.

>                 now = smum_get_argument(hwmgr);
>
>                 size += sprintf(buf + size, "0: %uMhz %s\n",
> -                               data->gfx_min_freq_limit / 100,
> -                               ((data->gfx_min_freq_limit / 100)
> -                                == now) ? "*" : "");
> -               size += sprintf(buf + size, "1: %uMhz %s\n",
> -                               data->gfx_max_freq_limit / 100,
> -                               ((data->gfx_max_freq_limit / 100)
> -                                == now) ? "*" : "");
> +                               now < SMU10_UMD_PSTATE_GFXCLK ? now : data->gfx_min_freq_limit/100,
> +                               now < SMU10_UMD_PSTATE_GFXCLK ? "*" : "");
> +               size += sprintf(buf + size, "1: %uMhz %s\n", SMU10_UMD_PSTATE_GFXCLK,
> +                               now == SMU10_UMD_PSTATE_GFXCLK ? "*" : "");
> +               size += sprintf(buf + size, "2: %uMhz %s\n",
> +                               now > SMU10_UMD_PSTATE_GFXCLK ? now : data->gfx_max_freq_limit/100,
> +                               now > SMU10_UMD_PSTATE_GFXCLK ? "*" : "");
>                 break;
>         case PP_MCLK:
>                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetFclkFrequency);
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.h b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.h
> index f68b218..1fb296a 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.h
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.h
> @@ -311,11 +311,9 @@ struct smu10_hwmgr {
>  #define SMU10_UMD_PSTATE_FCLK                   933
>  #define SMU10_UMD_PSTATE_VCE                    0x03C00320
>
> -#define SMU10_UMD_PSTATE_PEAK_GFXCLK            1100
>  #define SMU10_UMD_PSTATE_PEAK_SOCCLK            757
>  #define SMU10_UMD_PSTATE_PEAK_FCLK              1200
>
> -#define SMU10_UMD_PSTATE_MIN_GFXCLK             200
>  #define SMU10_UMD_PSTATE_MIN_FCLK               400
>  #define SMU10_UMD_PSTATE_MIN_SOCCLK             200
>  #define SMU10_UMD_PSTATE_MIN_VCE                0x0190012C
> --
> 1.9.1
>
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> amd-gfx at lists.freedesktop.org
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