On Wed, Apr 11, 2018 at 11:46:22AM +0800, Kenneth Feng wrote:
> pp_dpm_sclk/pp_dpm_mclk in sysfs implemented to force
> gfxclk/uclk dpm level for Vega12
>
> Change-Id: I69816de5da21de4264d3e6b6ead2c8ed3e00d742
> Signed-off-by: Kenneth Feng <kenneth.feng at amd.com>
For series: Reviewed-by: Huang Rui <ray.huang at amd.com>
> ---
> drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c | 42 +++++++++++++++++++++-
> 1 file changed, 41 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
> index 7dca75c..6fedc81 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
> @@ -991,15 +991,55 @@ static uint32_t vega12_find_highest_dpm_level(
>
> static int vega12_upload_dpm_min_level(struct pp_hwmgr *hwmgr)
> {
> + struct vega12_hwmgr *data = hwmgr->backend;
> + if (data->smc_state_table.gfx_boot_level !=
> + data->dpm_table.gfx_table.dpm_state.soft_min_level) {
> + smum_send_msg_to_smc_with_parameter(hwmgr,
> + PPSMC_MSG_SetSoftMinByFreq,
> + PP_SCLK<<16 | data->dpm_table.gfx_table.dpm_levels[data->smc_state_table.gfx_boot_level].value);
> + data->dpm_table.gfx_table.dpm_state.soft_min_level =
> + data->smc_state_table.gfx_boot_level;
> + }
> +
> + if (data->smc_state_table.mem_boot_level !=
> + data->dpm_table.mem_table.dpm_state.soft_min_level) {
> + smum_send_msg_to_smc_with_parameter(hwmgr,
> + PPSMC_MSG_SetSoftMinByFreq,
> + (PP_MCLK+4)<<16 | data->dpm_table.mem_table.dpm_levels[data->smc_state_table.mem_boot_level].value);
> + data->dpm_table.mem_table.dpm_state.soft_min_level =
> + data->smc_state_table.mem_boot_level;
> + }
> +
> return 0;
> +
> }
>
> static int vega12_upload_dpm_max_level(struct pp_hwmgr *hwmgr)
> {
> + struct vega12_hwmgr *data = hwmgr->backend;
> + if (data->smc_state_table.gfx_max_level !=
> + data->dpm_table.gfx_table.dpm_state.soft_max_level) {
> + smum_send_msg_to_smc_with_parameter(hwmgr,
> + PPSMC_MSG_SetSoftMaxByFreq,
> + /* plus the vale by 1 to align the resolution */
> + PP_SCLK<<16 | (data->dpm_table.gfx_table.dpm_levels[data->smc_state_table.gfx_max_level].value + 1));
> + data->dpm_table.gfx_table.dpm_state.soft_max_level =
> + data->smc_state_table.gfx_max_level;
> + }
> +
> + if (data->smc_state_table.mem_max_level !=
> + data->dpm_table.mem_table.dpm_state.soft_max_level) {
> + smum_send_msg_to_smc_with_parameter(hwmgr,
> + PPSMC_MSG_SetSoftMaxByFreq,
> + /* plus the vale by 1 to align the resolution */
> + (PP_MCLK+4)<<16 | (data->dpm_table.mem_table.dpm_levels[data->smc_state_table.mem_max_level].value + 1));
> + data->dpm_table.mem_table.dpm_state.soft_max_level =
> + data->smc_state_table.mem_max_level;
> + }
> +
> return 0;
> }
>
> -
> int vega12_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable)
> {
> struct vega12_hwmgr *data =
> --
> 2.7.4
>
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