On Wed, Apr 4, 2018 at 12:41 AM, Rex Zhu <Rex.Zhu at amd.com> wrote:
> In order to share pp_atomfwctrl_get_vbios_bootup_values
> on asics with different BIOS_CLKID.
> Not call function pp_atomfwctrl_get_clk_information_by_clkid in
> pp_atomfwctrl_get_vbios_bootup_values.
>
> Signed-off-by: Rex Zhu <Rex.Zhu at amd.com>
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
> ---
> drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c | 9 +--------
> drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.h | 2 ++
> drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 6 ++++++
> 3 files changed, 9 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c b/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c
> index 0adaf36..c97b0e5 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c
> @@ -488,7 +488,7 @@ int pp_atomfwctrl_get_gpio_information(struct pp_hwmgr *hwmgr,
> return 0;
> }
>
> -int pp_atomfwctrl__get_clk_information_by_clkid(struct pp_hwmgr *hwmgr, BIOS_CLKID id, uint32_t *frequency)
> +int pp_atomfwctrl_get_clk_information_by_clkid(struct pp_hwmgr *hwmgr, BIOS_CLKID id, uint32_t *frequency)
> {
> struct amdgpu_device *adev = hwmgr->adev;
> struct atom_get_smu_clock_info_parameters_v3_1 parameters;
> @@ -515,7 +515,6 @@ int pp_atomfwctrl_get_vbios_bootup_values(struct pp_hwmgr *hwmgr,
> {
> struct atom_firmware_info_v3_1 *info = NULL;
> uint16_t ix;
> - uint32_t frequency = 0;
>
> ix = GetIndexIntoMasterDataTable(firmwareinfo);
> info = (struct atom_firmware_info_v3_1 *)
> @@ -538,12 +537,6 @@ int pp_atomfwctrl_get_vbios_bootup_values(struct pp_hwmgr *hwmgr,
> boot_values->ulSocClk = 0;
> boot_values->ulDCEFClk = 0;
>
> - if (!pp_atomfwctrl__get_clk_information_by_clkid(hwmgr, SMU9_SYSPLL0_SOCCLK_ID, &frequency))
> - boot_values->ulSocClk = frequency;
> -
> - if (!pp_atomfwctrl__get_clk_information_by_clkid(hwmgr, SMU9_SYSPLL0_DCEFCLK_ID, &frequency))
> - boot_values->ulDCEFClk = frequency;
> -
> return 0;
> }
>
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.h b/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.h
> index 8df1e84f..fe10aa4 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.h
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.h
> @@ -230,6 +230,8 @@ int pp_atomfwctrl_get_vbios_bootup_values(struct pp_hwmgr *hwmgr,
> struct pp_atomfwctrl_bios_boot_up_values *boot_values);
> int pp_atomfwctrl_get_smc_dpm_information(struct pp_hwmgr *hwmgr,
> struct pp_atomfwctrl_smc_dpm_parameters *param);
> +int pp_atomfwctrl_get_clk_information_by_clkid(struct pp_hwmgr *hwmgr,
> + BIOS_CLKID id, uint32_t *frequency);
>
> #endif
>
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> index c9fb4b2..ba29942 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> @@ -2481,6 +2481,12 @@ static int vega10_init_smc_table(struct pp_hwmgr *hwmgr)
> data->vbios_boot_state.mvddc = boot_up_values.usMvddc;
> data->vbios_boot_state.gfx_clock = boot_up_values.ulGfxClk;
> data->vbios_boot_state.mem_clock = boot_up_values.ulUClk;
> + pp_atomfwctrl_get_clk_information_by_clkid(hwmgr,
> + SMU9_SYSPLL0_SOCCLK_ID, &boot_up_values.ulSocClk);
> +
> + pp_atomfwctrl_get_clk_information_by_clkid(hwmgr,
> + SMU9_SYSPLL0_DCEFCLK_ID, &boot_up_values.ulDCEFClk);
> +
> data->vbios_boot_state.soc_clock = boot_up_values.ulSocClk;
> data->vbios_boot_state.dcef_clock = boot_up_values.ulDCEFClk;
> if (0 != boot_up_values.usVddc) {
> --
> 1.9.1
>
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