On 2018-04-03 04:21 PM, Leo Liu wrote:
>
>
> On 04/03/2018 03:48 PM, James Zhu wrote:
>>
>>
>> On 2018-04-03 03:14 PM, Leo Liu wrote:
>>>
>>>
>>> On 04/03/2018 03:02 PM, James Zhu wrote:
>>>> Signed-off-by: James Zhu <James.Zhu at amd.com>
>>>> ---
>>>>  tests/amdgpu/Makefile.am   |  1 +
>>>>  tests/amdgpu/amdgpu_test.c | 11 +
>>>>  tests/amdgpu/amdgpu_test.h | 20 ++
>>>>  tests/amdgpu/vce_ib.h      | 21 +-
>>>> Â tests/amdgpu/vce_mv_tests.c | 537
>>>> ++++++++++++++++++++++++++++++++++++++++++++
>>>> Â 5 files changed, 588 insertions(+), 2 deletions(-)
>>>> Â create mode 100644 tests/amdgpu/vce_mv_tests.c
>>>>
>>>> diff --git a/tests/amdgpu/Makefile.am b/tests/amdgpu/Makefile.am
>>>> index e79c1bd..8e5e4c1 100644
>>>> --- a/tests/amdgpu/Makefile.am
>>>> +++ b/tests/amdgpu/Makefile.am
>>>> @@ -26,6 +26,7 @@ amdgpu_test_SOURCES = \
>>>> Â Â Â Â Â cs_tests.c \
>>>> Â Â Â Â Â decode_messages.h \
>>>> Â Â Â Â Â vce_tests.c \
>>>> +Â Â Â vce_mv_tests.c \
>>>> Â Â Â Â Â vce_ib.h \
>>>> Â Â Â Â Â frame.h \
>>>> Â Â Â Â Â uvd_enc_tests.c \
>>>> diff --git a/tests/amdgpu/amdgpu_test.c b/tests/amdgpu/amdgpu_test.c
>>>> index 96fcd68..08fe94b 100644
>>>> --- a/tests/amdgpu/amdgpu_test.c
>>>> +++ b/tests/amdgpu/amdgpu_test.c
>>>> @@ -52,6 +52,7 @@
>>>> Â #define BO_TESTS_STR "BO Tests"
>>>> Â #define CS_TESTS_STR "CS Tests"
>>>> Â #define VCE_TESTS_STR "VCE Tests"
>>>> +#define VCE_MV_TESTS_STR "VCE MV Tests"
>>>> Â #define VCN_TESTS_STR "VCN Tests"
>>>> Â #define UVD_ENC_TESTS_STR "UVD ENC Tests"
>>>> Â #define DEADLOCK_TESTS_STR "Deadlock Tests"
>>>> @@ -93,6 +94,12 @@ static CU_SuiteInfo suites[] = {
>>>> Â Â Â Â Â Â Â Â Â .pTests = vce_tests,
>>>> Â Â Â Â Â },
>>>> Â Â Â Â Â {
>>>> +Â Â Â Â Â Â Â .pName = VCE_MV_TESTS_STR,
>>>> +Â Â Â Â Â Â Â .pInitFunc = suite_vce_mv_tests_init,
>>>> +Â Â Â Â Â Â Â .pCleanupFunc = suite_vce_mv_tests_clean,
>>>> +Â Â Â Â Â Â Â .pTests = vce_mv_tests,
>>>> +Â Â Â },
>>>> +Â Â Â {
>>>> Â Â Â Â Â Â Â Â Â .pName = VCN_TESTS_STR,
>>>> Â Â Â Â Â Â Â Â Â .pInitFunc = suite_vcn_tests_init,
>>>> Â Â Â Â Â Â Â Â Â .pCleanupFunc = suite_vcn_tests_clean,
>>>> @@ -150,6 +157,10 @@ static Suites_Active_Status
>>>> suites_active_stat[] = {
>>>> Â Â Â Â Â Â Â Â Â Â Â Â Â .pActive = suite_vce_tests_enable,
>>>> Â Â Â Â Â Â Â Â Â },
>>>> Â Â Â Â Â Â Â Â Â {
>>>> +Â Â Â Â Â Â Â Â Â Â Â .pName = VCE_MV_TESTS_STR,
>>>> +Â Â Â Â Â Â Â Â Â Â Â .pActive = suite_vce_mv_tests_enable,
>>>> +Â Â Â Â Â Â Â },
>>>> +Â Â Â Â Â Â Â {
>>>> Â Â Â Â Â Â Â Â Â Â Â Â Â .pName = VCN_TESTS_STR,
>>>> Â Â Â Â Â Â Â Â Â Â Â Â Â .pActive = suite_vcn_tests_enable,
>>>> Â Â Â Â Â Â Â Â Â },
>>>> diff --git a/tests/amdgpu/amdgpu_test.h b/tests/amdgpu/amdgpu_test.h
>>>> index 6287573..bf6e7d8 100644
>>>> --- a/tests/amdgpu/amdgpu_test.h
>>>> +++ b/tests/amdgpu/amdgpu_test.h
>>>> @@ -115,6 +115,26 @@ CU_BOOL suite_vce_tests_enable(void);
>>>> Â extern CU_TestInfo vce_tests[];
>>>> Â Â /**
>>>> + * Initialize vce test suite
>>>> + */
>>>> +int suite_vce_mv_tests_init();
>>>> +
>>>> +/**
>>>> + * Deinitialize vce test suite
>>>> + */
>>>> +int suite_vce_mv_tests_clean();
>>>> +
>>>> +/**
>>>> + * Decide if the suite is enabled by default or not.
>>>> + */
>>>> +CU_BOOL suite_vce_mv_tests_enable(void);
>>>> +
>>>> +/**
>>>> + * Tests in vce test suite
>>>> + */
>>>> +extern CU_TestInfo vce_mv_tests[];
>>>> +
>>>> +/**
>>>> Â + * Initialize vcn test suite
>>>> Â + */
>>>> Â int suite_vcn_tests_init();
>>>> diff --git a/tests/amdgpu/vce_ib.h b/tests/amdgpu/vce_ib.h
>>>> index 80ab179..cbdcc71 100644
>>>> --- a/tests/amdgpu/vce_ib.h
>>>> +++ b/tests/amdgpu/vce_ib.h
>>>> @@ -41,7 +41,7 @@ static uint32_t vce_taskinfo[8] = {
>>>> Â Â Â Â Â 0x00000000,
>>>> Â };
>>>> Â -static const uint32_t vce_create[] = {
>>>> +static uint32_t vce_create[] = {
>>>> Â Â Â Â Â 0x00000030,
>>>> Â Â Â Â Â 0x01000001,
>>>> Â Â Â Â Â 0x00000000,
>>>> @@ -144,7 +144,7 @@ static const uint32_t vce_rdo[] = {
>>>> Â Â Â Â Â 0x00000000,
>>>> Â };
>>>> Â -static const uint32_t vce_pic_ctrl[] = {
>>>> +static uint32_t vce_pic_ctrl[] = {
>>>> Â Â Â Â Â 0x00000074,
>>>> Â Â Â Â Â 0x04000002,
>>>> Â Â Â Â Â 0x00000000,
>>>> @@ -315,4 +315,21 @@ static const uint32_t vce_destroy[] = {
>>>> Â Â Â Â Â 0x00000008,
>>>> Â Â Â Â Â 0x02000001,
>>>> Â };
>>>> +
>>>> +static const uint32_t vce_mv_buffer[] = {
>>>> +Â Â Â 0x00000038,
>>>> +Â Â Â 0x0500000d,
>>>> +Â Â Â 0x00000000,
>>>> +Â Â Â 0x00000000,
>>>> +Â Â Â 0x00000000,
>>>> +Â Â Â 0x00000000,
>>>> +Â Â Â 0x00000000,
>>>> +Â Â Â 0x00000000,
>>>> +Â Â Â 0x00000000,
>>>> +Â Â Â 0x00000000,
>>>> +Â Â Â 0x00000000,
>>>> +Â Â Â 0x00000000,
>>>> +Â Â Â 0x00000000,
>>>> +Â Â Â 0x00000000,
>>>> +};
>>>> Â #endif /*_vce_ib_h*/
>>>> diff --git a/tests/amdgpu/vce_mv_tests.c b/tests/amdgpu/vce_mv_tests.c
>>>> new file mode 100644
>>>> index 0000000..89affb6
>>>> --- /dev/null
>>>> +++ b/tests/amdgpu/vce_mv_tests.c
>>>> @@ -0,0 +1,537 @@
>>>> +/*
>>>> + * Copyright 2018 Advanced Micro Devices, Inc.
>>>> + *
>>>> + * Permission is hereby granted, free of charge, to any person
>>>> obtaining a
>>>> + * copy of this software and associated documentation files (the
>>>> "Software"),
>>>> + * to deal in the Software without restriction, including without
>>>> limitation
>>>> + * the rights to use, copy, modify, merge, publish, distribute,
>>>> sublicense,
>>>> + * and/or sell copies of the Software, and to permit persons to
>>>> whom the
>>>> + * Software is furnished to do so, subject to the following
>>>> conditions:
>>>> + *
>>>> + * The above copyright notice and this permission notice shall be
>>>> included in
>>>> + * all copies or substantial portions of the Software.
>>>> + *
>>>> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
>>>> EXPRESS OR
>>>> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
>>>> MERCHANTABILITY,
>>>> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO
>>>> EVENT SHALL
>>>> + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM,
>>>> DAMAGES OR
>>>> + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
>>>> OTHERWISE,
>>>> + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
>>>> USE OR
>>>> + * OTHER DEALINGS IN THE SOFTWARE.
>>>> + *
>>>> +*/
>>>> +
>>>> +#include <stdio.h>
>>>> +#include <inttypes.h>
>>>> +
>>>> +#include "CUnit/Basic.h"
>>>> +
>>>> +#include "util_math.h"
>>>> +
>>>> +#include "amdgpu_test.h"
>>>> +#include "amdgpu_drm.h"
>>>> +#include "amdgpu_internal.h"
>>>> +
>>>> +#include "vce_ib.h"
>>>> +#include "frame.h"
>>>> +
>>>> +#define IB_SIZEÂ Â Â Â Â Â Â 4096
>>>> +#define MAX_RESOURCESÂ Â Â 16
>>>> +#define FW_53_0_03 ((53 << 24) | (0 << 16) | (03 << 8))
>>>> +
>>>> +struct amdgpu_vce_bo {
>>>> +Â Â Â amdgpu_bo_handle handle;
>>>> +Â Â Â amdgpu_va_handle va_handle;
>>>> +Â Â Â uint64_t addr;
>>>> +Â Â Â uint64_t size;
>>>> +Â Â Â uint8_t *ptr;
>>>> +};
>>>> +
>>>> +struct amdgpu_vce_encode {
>>>> +Â Â Â unsigned width;
>>>> +Â Â Â unsigned height;
>>>> +Â Â Â struct amdgpu_vce_bo vbuf;
>>>> +Â Â Â struct amdgpu_vce_bo bs;
>>>> +Â Â Â struct amdgpu_vce_bo fb;
>>>> +Â Â Â struct amdgpu_vce_bo mvrefbuf;
>>>> +Â Â Â struct amdgpu_vce_bo mvb;
>>>> +Â Â Â struct amdgpu_vce_bo cpb;
>>>> +Â Â Â unsigned mvbuf_size;
>>>> +Â Â Â unsigned ib_len;
>>>> +};
>>>> +
>>>> +static amdgpu_device_handle device_handle;
>>>> +static uint32_t major_version;
>>>> +static uint32_t minor_version;
>>>> +static uint32_t family_id;
>>>> +static uint32_t chip_rev;
>>>> +static uint32_t chip_id;
>>>> +static uint32_t ids_flags;
>>>> +
>>>> +static amdgpu_context_handle context_handle;
>>>> +static amdgpu_bo_handle ib_handle;
>>>> +static amdgpu_va_handle ib_va_handle;
>>>> +static uint64_t ib_mc_address;
>>>> +static uint32_t *ib_cpu;
>>>> +
>>>> +static struct amdgpu_vce_encode enc;
>>>> +static amdgpu_bo_handle resources[MAX_RESOURCES];
>>>> +static unsigned num_resources;
>>>> +
>>>> +static void amdgpu_cs_vce_create(void);
>>>> +static void amdgpu_cs_vce_encode_mv(void);
>>>> +static void amdgpu_cs_vce_destroy(void);
>>>> +
>>>> +CU_TestInfo vce_mv_tests[] = {
>>>> +   { "VCE create", amdgpu_cs_vce_create },
>>>> +   { "VCE mvdump", amdgpu_cs_vce_encode_mv },
>>>> +   { "VCE destroy", amdgpu_cs_vce_destroy },
>>> Why does it need to have a separated file, and many duplicated stuff
>>> from vce_tests.c ?
>>>
>>> Regards,
>>> Leo
>>>
>> If we put them together. add one test set: { "VCE MV",
>> amdgpu_cs_vce_mv_encode } in current vce test, this test must be
>> execute no matter the asic support or not.
>> No way to bypass. If we always return success if the asic doesn't
>> support, it looks weird.
> I think you could print "Not support" and bypass it with return
> success, since MV test should belong to one of the VCE tests.
>
> Regards,
> Leo
>
Found a API to bypass the specified test dynamically. I will combine the
two test suit together,
Best Regards!
James Zhu
>> If you don't matter this, I can combine them together.
>>
>> Best Regards!
>> James zhu
>>
>>>
>>>> +Â Â Â CU_TEST_INFO_NULL,
>>>> +};
>>>> +
>>>> +CU_BOOL suite_vce_mv_tests_enable(void)
>>>> +{
>>>> +Â Â Â uint32_t version, feature;
>>>> +
>>>> +Â Â Â if (amdgpu_device_initialize(drm_amdgpu[0], &major_version,
>>>> +Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â &minor_version, &device_handle))
>>>> +Â Â Â Â Â Â Â return CU_FALSE;
>>>> +
>>>> +Â Â Â family_id = device_handle->info.family_id;
>>>> +Â Â Â chip_rev = device_handle->info.chip_rev;
>>>> +Â Â Â chip_id = device_handle->info.chip_external_rev;
>>>> +Â Â Â ids_flags = device_handle->info.ids_flags;
>>>> +
>>>> +Â Â Â amdgpu_query_firmware_version(device_handle,
>>>> AMDGPU_INFO_FW_VCE, 0,
>>>> +Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â 0, &version, &feature);
>>>> +
>>>> +Â Â Â if (amdgpu_device_deinitialize(device_handle))
>>>> +Â Â Â Â Â Â Â return CU_FALSE;
>>>> +
>>>> +Â Â Â if (family_id >= AMDGPU_FAMILY_RV || family_id ==
>>>> AMDGPU_FAMILY_SI) {
>>>> +Â Â Â Â Â Â Â printf("\n\nThe ASIC family NOT support VCE MV, suite
>>>> disabled\n");
>>>> +Â Â Â Â Â Â Â return CU_FALSE;
>>>> +Â Â Â }
>>>> +
>>>> +Â Â Â if (!(chip_id == (chip_rev + 0x14) || /* TONGA */
>>>> +Â Â Â Â Â Â Â Â Â Â Â chip_id == (chip_rev + 0x3C) || /* FIJI */
>>>> +Â Â Â Â Â Â Â Â Â Â Â chip_id == (chip_rev + 0x50) || /* Polaris 10*/
>>>> +Â Â Â Â Â Â Â Â Â Â Â chip_id == (chip_rev + 0x5A) || /* Polaris 11*/
>>>> +Â Â Â Â Â Â Â Â Â Â Â chip_id == (chip_rev + 0x64) || /* Polaris 12*/
>>>> +Â Â Â Â Â Â Â Â Â Â Â (family_id > AMDGPU_FAMILY_VI && !ids_flags))) /* dGPU
>>>> > Polaris */{
>>>> +Â Â Â Â Â Â Â printf("\n\nThe ASIC NOT support VCE MV, suite disabled\n");
>>>> +Â Â Â Â Â Â Â return CU_FALSE;
>>>> +Â Â Â }
>>>> +
>>>> +Â Â Â if (FW_53_0_03 >= version){
>>>> +Â Â Â Â Â Â Â printf("\n\nThe ASIC FW version NOT support VCE MV, suite
>>>> disabled\n");
>>>> +Â Â Â Â Â Â Â return CU_FALSE;
>>>> +Â Â Â }
>>>> +Â Â Â return CU_TRUE;
>>>> +}
>>>> +
>>>> +int suite_vce_mv_tests_init(void)
>>>> +{
>>>> +Â Â Â int r;
>>>> +
>>>> +Â Â Â r = amdgpu_device_initialize(drm_amdgpu[0], &major_version,
>>>> +Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â &minor_version, &device_handle);
>>>> +Â Â Â if (r) {
>>>> +Â Â Â Â Â Â Â if ((r == -EACCES) && (errno == EACCES))
>>>> +Â Â Â Â Â Â Â Â Â Â Â printf("\n\nError:%s. "
>>>> +Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â "Hint:Try to run this test program as root.",
>>>> +Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â strerror(errno));
>>>> +
>>>> +Â Â Â Â Â Â Â return CUE_SINIT_FAILED;
>>>> +Â Â Â }
>>>> +
>>>> +Â Â Â family_id = device_handle->info.family_id;
>>>> +
>>>> +Â Â Â r = amdgpu_cs_ctx_create(device_handle, &context_handle);
>>>> +Â Â Â if (r)
>>>> +Â Â Â Â Â Â Â return CUE_SINIT_FAILED;
>>>> +
>>>> +Â Â Â r = amdgpu_bo_alloc_and_map(device_handle, IB_SIZE, 4096,
>>>> +Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â AMDGPU_GEM_DOMAIN_GTT, 0,
>>>> +Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â &ib_handle, (void**)&ib_cpu,
>>>> +Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â &ib_mc_address, &ib_va_handle);
>>>> +Â Â Â if (r)
>>>> +Â Â Â Â Â Â Â return CUE_SINIT_FAILED;
>>>> +
>>>> +Â Â Â memset(&enc, 0, sizeof(struct amdgpu_vce_encode));
>>>> +
>>>> +Â Â Â return CUE_SUCCESS;
>>>> +}
>>>> +
>>>> +int suite_vce_mv_tests_clean(void)
>>>> +{
>>>> +Â Â Â int r;
>>>> +
>>>> +Â Â Â r = amdgpu_bo_unmap_and_free(ib_handle, ib_va_handle,
>>>> +Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â ib_mc_address, IB_SIZE);
>>>> +Â Â Â if (r)
>>>> +Â Â Â Â Â Â Â return CUE_SCLEAN_FAILED;
>>>> +
>>>> +Â Â Â r = amdgpu_cs_ctx_free(context_handle);
>>>> +Â Â Â if (r)
>>>> +Â Â Â Â Â Â Â return CUE_SCLEAN_FAILED;
>>>> +
>>>> +Â Â Â r = amdgpu_device_deinitialize(device_handle);
>>>> +Â Â Â if (r)
>>>> +Â Â Â Â Â Â Â return CUE_SCLEAN_FAILED;
>>>> +
>>>> +Â Â Â return CUE_SUCCESS;
>>>> +}
>>>> +
>>>> +static int submit(unsigned ndw, unsigned ip)
>>>> +{
>>>> +Â Â Â struct amdgpu_cs_request ibs_request = {0};
>>>> +Â Â Â struct amdgpu_cs_ib_info ib_info = {0};
>>>> +Â Â Â struct amdgpu_cs_fence fence_status = {0};
>>>> +Â Â Â uint32_t expired;
>>>> +Â Â Â int r;
>>>> +
>>>> +Â Â Â ib_info.ib_mc_address = ib_mc_address;
>>>> +Â Â Â ib_info.size = ndw;
>>>> +
>>>> +Â Â Â ibs_request.ip_type = ip;
>>>> +
>>>> +Â Â Â r = amdgpu_bo_list_create(device_handle, num_resources,
>>>> resources,
>>>> +Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â NULL, &ibs_request.resources);
>>>> +Â Â Â if (r)
>>>> +Â Â Â Â Â Â Â return r;
>>>> +
>>>> +Â Â Â ibs_request.number_of_ibs = 1;
>>>> +Â Â Â ibs_request.ibs = &ib_info;
>>>> +Â Â Â ibs_request.fence_info.handle = NULL;
>>>> +
>>>> +Â Â Â r = amdgpu_cs_submit(context_handle, 0, &ibs_request, 1);
>>>> +Â Â Â if (r)
>>>> +Â Â Â Â Â Â Â return r;
>>>> +
>>>> +Â Â Â r = amdgpu_bo_list_destroy(ibs_request.resources);
>>>> +Â Â Â if (r)
>>>> +Â Â Â Â Â Â Â return r;
>>>> +
>>>> +Â Â Â fence_status.context = context_handle;
>>>> +Â Â Â fence_status.ip_type = ip;
>>>> +Â Â Â fence_status.fence = ibs_request.seq_no;
>>>> +
>>>> +Â Â Â r = amdgpu_cs_query_fence_status(&fence_status,
>>>> +Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â AMDGPU_TIMEOUT_INFINITE,
>>>> +Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â 0, &expired);
>>>> +Â Â Â if (r)
>>>> +Â Â Â Â Â Â Â return r;
>>>> +
>>>> +Â Â Â return 0;
>>>> +}
>>>> +
>>>> +static void alloc_resource(struct amdgpu_vce_bo *vce_bo, unsigned
>>>> size, unsigned domain)
>>>> +{
>>>> +Â Â Â struct amdgpu_bo_alloc_request req = {0};
>>>> +Â Â Â amdgpu_bo_handle buf_handle;
>>>> +Â Â Â amdgpu_va_handle va_handle;
>>>> +Â Â Â uint64_t va = 0;
>>>> +Â Â Â int r;
>>>> +
>>>> +Â Â Â req.alloc_size = ALIGN(size, 4096);
>>>> +Â Â Â req.preferred_heap = domain;
>>>> +Â Â Â r = amdgpu_bo_alloc(device_handle, &req, &buf_handle);
>>>> +Â Â Â CU_ASSERT_EQUAL(r, 0);
>>>> +Â Â Â r = amdgpu_va_range_alloc(device_handle,
>>>> +Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â amdgpu_gpu_va_range_general,
>>>> +Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â req.alloc_size, 1, 0, &va,
>>>> +Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â &va_handle, 0);
>>>> +Â Â Â CU_ASSERT_EQUAL(r, 0);
>>>> +Â Â Â r = amdgpu_bo_va_op(buf_handle, 0, req.alloc_size, va, 0,
>>>> +Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â AMDGPU_VA_OP_MAP);
>>>> +Â Â Â CU_ASSERT_EQUAL(r, 0);
>>>> +Â Â Â vce_bo->addr = va;
>>>> +Â Â Â vce_bo->handle = buf_handle;
>>>> +Â Â Â vce_bo->size = req.alloc_size;
>>>> +Â Â Â vce_bo->va_handle = va_handle;
>>>> +Â Â Â r = amdgpu_bo_cpu_map(vce_bo->handle, (void **)&vce_bo->ptr);
>>>> +Â Â Â CU_ASSERT_EQUAL(r, 0);
>>>> +Â Â Â memset(vce_bo->ptr, 0, size);
>>>> +Â Â Â r = amdgpu_bo_cpu_unmap(vce_bo->handle);
>>>> +Â Â Â CU_ASSERT_EQUAL(r, 0);
>>>> +}
>>>> +
>>>> +static void free_resource(struct amdgpu_vce_bo *vce_bo)
>>>> +{
>>>> +Â Â Â int r;
>>>> +
>>>> +Â Â Â r = amdgpu_bo_va_op(vce_bo->handle, 0, vce_bo->size,
>>>> +Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â vce_bo->addr, 0, AMDGPU_VA_OP_UNMAP);
>>>> +Â Â Â CU_ASSERT_EQUAL(r, 0);
>>>> +
>>>> +Â Â Â r = amdgpu_va_range_free(vce_bo->va_handle);
>>>> +Â Â Â CU_ASSERT_EQUAL(r, 0);
>>>> +
>>>> +Â Â Â r = amdgpu_bo_free(vce_bo->handle);
>>>> +Â Â Â CU_ASSERT_EQUAL(r, 0);
>>>> +Â Â Â memset(vce_bo, 0, sizeof(*vce_bo));
>>>> +}
>>>> +
>>>> +static void amdgpu_cs_vce_create(void)
>>>> +{
>>>> +Â Â Â unsigned align = (family_id >= AMDGPU_FAMILY_AI) ? 256 : 16;
>>>> +Â Â Â int len, r;
>>>> +
>>>> +Â Â Â vce_create[11] = 0x01000000;Â Â /* disableTwoInstance */
>>>> +Â Â Â vce_pic_ctrl[27] = 0x00000001; /* encSliceMode */
>>>> +
>>>> +Â Â Â enc.width = vce_create[6];
>>>> +Â Â Â enc.height = vce_create[7];
>>>> +
>>>> +   num_resources = 0;
>>>> +Â Â Â alloc_resource(&enc.fb, 4096, AMDGPU_GEM_DOMAIN_GTT);
>>>> +Â Â Â resources[num_resources++] = enc.fb.handle;
>>>> +Â Â Â resources[num_resources++] = ib_handle;
>>>> +
>>>> +Â Â Â len = 0;
>>>> +Â Â Â memcpy(ib_cpu, vce_session, sizeof(vce_session));
>>>> +Â Â Â len += sizeof(vce_session) / 4;
>>>> +Â Â Â memcpy((ib_cpu + len), vce_taskinfo, sizeof(vce_taskinfo));
>>>> +Â Â Â len += sizeof(vce_taskinfo) / 4;
>>>> +Â Â Â memcpy((ib_cpu + len), vce_create, sizeof(vce_create));
>>>> +Â Â Â ib_cpu[len + 8] = ALIGN(enc.width, align);
>>>> +Â Â Â ib_cpu[len + 9] = ALIGN(enc.width, align);
>>>> +Â Â Â len += sizeof(vce_create) / 4;
>>>> +Â Â Â memcpy((ib_cpu + len), vce_feedback, sizeof(vce_feedback));
>>>> +Â Â Â ib_cpu[len + 2] = enc.fb.addr >> 32;
>>>> +Â Â Â ib_cpu[len + 3] = enc.fb.addr;
>>>> +Â Â Â len += sizeof(vce_feedback) / 4;
>>>> +
>>>> +Â Â Â r = submit(len, AMDGPU_HW_IP_VCE);
>>>> +Â Â Â CU_ASSERT_EQUAL(r, 0);
>>>> +
>>>> +Â Â Â free_resource(&enc.fb);
>>>> +}
>>>> +
>>>> +static void amdgpu_cs_vce_config(void)
>>>> +{
>>>> +Â Â Â int len = 0, r;
>>>> +
>>>> +Â Â Â memcpy((ib_cpu + len), vce_session, sizeof(vce_session));
>>>> +Â Â Â len += sizeof(vce_session) / 4;
>>>> +Â Â Â memcpy((ib_cpu + len), vce_taskinfo, sizeof(vce_taskinfo));
>>>> +Â Â Â ib_cpu[len + 3] = 2;
>>>> +Â Â Â ib_cpu[len + 6] = 0xffffffff;
>>>> +Â Â Â len += sizeof(vce_taskinfo) / 4;
>>>> +Â Â Â memcpy((ib_cpu + len), vce_rate_ctrl, sizeof(vce_rate_ctrl));
>>>> +Â Â Â len += sizeof(vce_rate_ctrl) / 4;
>>>> +Â Â Â memcpy((ib_cpu + len), vce_config_ext, sizeof(vce_config_ext));
>>>> +Â Â Â len += sizeof(vce_config_ext) / 4;
>>>> +Â Â Â memcpy((ib_cpu + len), vce_motion_est, sizeof(vce_motion_est));
>>>> +Â Â Â len += sizeof(vce_motion_est) / 4;
>>>> +Â Â Â memcpy((ib_cpu + len), vce_rdo, sizeof(vce_rdo));
>>>> +Â Â Â len += sizeof(vce_rdo) / 4;
>>>> +Â Â Â memcpy((ib_cpu + len), vce_pic_ctrl, sizeof(vce_pic_ctrl));
>>>> +Â Â Â len += sizeof(vce_pic_ctrl) / 4;
>>>> +
>>>> +Â Â Â r = submit(len, AMDGPU_HW_IP_VCE);
>>>> +Â Â Â CU_ASSERT_EQUAL(r, 0);
>>>> +}
>>>> +
>>>> +static void amdgpu_cs_vce_mv(struct amdgpu_vce_encode *enc)
>>>> +{
>>>> +Â Â Â uint64_t luma_offset, chroma_offset;
>>>> +Â Â Â uint64_t mv_ref_luma_offset;
>>>> +Â Â Â unsigned align = (family_id >= AMDGPU_FAMILY_AI) ? 256 : 16;
>>>> +Â Â Â unsigned luma_size = ALIGN(enc->width, align) *
>>>> ALIGN(enc->height, 16);
>>>> +Â Â Â int len = 0, i, r;
>>>> +
>>>> +Â Â Â luma_offset = enc->vbuf.addr;
>>>> +Â Â Â chroma_offset = luma_offset + luma_size;
>>>> +Â Â Â mv_ref_luma_offset = enc->mvrefbuf.addr;
>>>> +
>>>> +Â Â Â memcpy((ib_cpu + len), vce_session, sizeof(vce_session));
>>>> +Â Â Â len += sizeof(vce_session) / 4;
>>>> +Â Â Â memcpy((ib_cpu + len), vce_taskinfo, sizeof(vce_taskinfo));
>>>> +Â Â Â len += sizeof(vce_taskinfo) / 4;
>>>> +Â Â Â memcpy((ib_cpu + len), vce_bs_buffer, sizeof(vce_bs_buffer));
>>>> +Â Â Â ib_cpu[len + 2] = enc->bs.addr >> 32;
>>>> +Â Â Â ib_cpu[len + 3] = enc->bs.addr;
>>>> +Â Â Â len += sizeof(vce_bs_buffer) / 4;
>>>> +Â Â Â memcpy((ib_cpu + len), vce_context_buffer,
>>>> sizeof(vce_context_buffer));
>>>> +Â Â Â ib_cpu[len + 2] = enc->cpb.addr >> 32;
>>>> +Â Â Â ib_cpu[len + 3] = enc->cpb.addr;
>>>> +Â Â Â len += sizeof(vce_context_buffer) / 4;
>>>> +Â Â Â memcpy((ib_cpu + len), vce_aux_buffer, sizeof(vce_aux_buffer));
>>>> +Â Â Â for (i = 0; i <Â 8; ++i)
>>>> +Â Â Â Â Â Â Â ib_cpu[len + 2 + i] = luma_size * 1.5 * (i + 2);
>>>> +Â Â Â for (i = 0; i <Â 8; ++i)
>>>> +Â Â Â Â Â Â Â ib_cpu[len + 10 + i] = luma_size * 1.5;
>>>> +Â Â Â len += sizeof(vce_aux_buffer) / 4;
>>>> +Â Â Â memcpy((ib_cpu + len), vce_feedback, sizeof(vce_feedback));
>>>> +Â Â Â ib_cpu[len + 2] = enc->fb.addr >> 32;
>>>> +Â Â Â ib_cpu[len + 3] = enc->fb.addr;
>>>> +Â Â Â len += sizeof(vce_feedback) / 4;
>>>> +Â Â Â memcpy((ib_cpu + len), vce_mv_buffer, sizeof(vce_mv_buffer));
>>>> +Â Â Â ib_cpu[len + 2] = mv_ref_luma_offset >> 32;
>>>> +Â Â Â ib_cpu[len + 3] = mv_ref_luma_offset;
>>>> +Â Â Â ib_cpu[len + 4] = ALIGN(enc->width, align);
>>>> +Â Â Â ib_cpu[len + 5] = ALIGN(enc->width, align);
>>>> +Â Â Â ib_cpu[len + 6] = luma_size;
>>>> +Â Â Â ib_cpu[len + 7] = enc->mvb.addr >> 32;
>>>> +Â Â Â ib_cpu[len + 8] = enc->mvb.addr;
>>>> +Â Â Â len += sizeof(vce_mv_buffer) / 4;
>>>> +Â Â Â memcpy((ib_cpu + len), vce_encode, sizeof(vce_encode));
>>>> +Â Â Â ib_cpu[len + 2] = 0;
>>>> +Â Â Â ib_cpu[len + 3] = 0;
>>>> +Â Â Â ib_cpu[len + 4] = 0x154000;
>>>> +Â Â Â ib_cpu[len + 9] = luma_offset >> 32;
>>>> +Â Â Â ib_cpu[len + 10] = luma_offset;
>>>> +Â Â Â ib_cpu[len + 11] = chroma_offset >> 32;
>>>> +Â Â Â ib_cpu[len + 12] = chroma_offset;
>>>> +Â Â Â ib_cpu[len + 13] = ALIGN(enc->height, 16);;
>>>> +Â Â Â ib_cpu[len + 14] = ALIGN(enc->width, align);
>>>> +Â Â Â ib_cpu[len + 15] = ALIGN(enc->width, align);
>>>> +Â Â Â /*
>>>> encDisableMBOffloading-encDisableTwoPipeMode-encInputPicArrayMode-encInputPicAddrMode
>>>> */
>>>> +Â Â Â ib_cpu[len + 16] = 0x01010000;
>>>> +Â Â Â ib_cpu[len + 18] = 0; /* encPicType */
>>>> +Â Â Â ib_cpu[len + 19] = 0; /* encIdrFlag */
>>>> +Â Â Â ib_cpu[len + 20] = 0; /* encIdrPicId */
>>>> +Â Â Â ib_cpu[len + 21] = 0; /* encMGSKeyPic */
>>>> +Â Â Â ib_cpu[len + 22] = 0; /* encReferenceFlag */
>>>> +Â Â Â ib_cpu[len + 23] = 0; /* encTemporalLayerIndex */
>>>> +Â Â Â ib_cpu[len + 55] = 0; /* pictureStructure */
>>>> +Â Â Â ib_cpu[len + 56] = 0; /* encPicType -ref[0] */
>>>> +Â Â Â ib_cpu[len + 61] = 0; /* pictureStructure */
>>>> +Â Â Â ib_cpu[len + 62] = 0; /* encPicType -ref[1] */
>>>> +Â Â Â ib_cpu[len + 67] = 0; /* pictureStructure */
>>>> +Â Â Â ib_cpu[len + 68] = 0; /* encPicType -ref1 */
>>>> +Â Â Â ib_cpu[len + 81] = 1; /* frameNumber */
>>>> +Â Â Â ib_cpu[len + 82] = 2; /* pictureOrderCount */
>>>> +Â Â Â ib_cpu[len + 83] = 0xffffffff; /* numIPicRemainInRCGOP */
>>>> +Â Â Â ib_cpu[len + 84] = 0xffffffff; /* numPPicRemainInRCGOP */
>>>> +Â Â Â ib_cpu[len + 85] = 0xffffffff; /* numBPicRemainInRCGOP */
>>>> +Â Â Â ib_cpu[len + 86] = 0xffffffff; /* numIRPicRemainInRCGOP */
>>>> +Â Â Â ib_cpu[len + 87] = 0; /* remainedIntraRefreshPictures */
>>>> +Â Â Â len += sizeof(vce_encode) / 4;
>>>> +
>>>> +Â Â Â enc->ib_len = len;
>>>> +Â Â Â r = submit(len, AMDGPU_HW_IP_VCE);
>>>> +Â Â Â CU_ASSERT_EQUAL(r, 0);
>>>> +}
>>>> +
>>>> +static void check_mv_result(struct amdgpu_vce_encode *enc)
>>>> +{
>>>> +Â Â Â uint64_t sum;
>>>> +Â Â Â uint32_t s = 140790;
>>>> +Â Â Â uint32_t *ptr, size;
>>>> +Â Â Â int i, j, r;
>>>> +
>>>> +Â Â Â r = amdgpu_bo_cpu_map(enc->fb.handle, (void **)&enc->fb.ptr);
>>>> +Â Â Â CU_ASSERT_EQUAL(r, 0);
>>>> +Â Â Â ptr = (uint32_t *)enc->fb.ptr;
>>>> +Â Â Â r = amdgpu_bo_cpu_unmap(enc->fb.handle);
>>>> +Â Â Â CU_ASSERT_EQUAL(r, 0);
>>>> +Â Â Â r = amdgpu_bo_cpu_map(enc->mvb.handle, (void **)&enc->mvb.ptr);
>>>> +Â Â Â CU_ASSERT_EQUAL(r, 0);
>>>> +Â Â Â for (j = 0, sum = 0; j < enc->mvbuf_size; ++j)
>>>> +Â Â Â Â Â Â Â sum += enc->mvb.ptr[j];
>>>> +Â Â Â CU_ASSERT_EQUAL(sum, s);
>>>> +Â Â Â r = amdgpu_bo_cpu_unmap(enc->mvb.handle);
>>>> +Â Â Â CU_ASSERT_EQUAL(r, 0);
>>>> +}
>>>> +
>>>> +static void amdgpu_cs_vce_encode_mv(void)
>>>> +{
>>>> +Â Â Â uint32_t vbuf_size, bs_size = 0x154000, cpb_size;
>>>> +Â Â Â unsigned align = (family_id >= AMDGPU_FAMILY_AI) ? 256 : 16;
>>>> +Â Â Â int i, r;
>>>> +
>>>> +Â Â Â vbuf_size = ALIGN(enc.width, align) * ALIGN(enc.height, 16) *
>>>> 1.5;
>>>> +Â Â Â enc.mvbuf_size = ALIGN(enc.width, 16) * ALIGN(enc.height, 16)
>>>> / 8;
>>>> +Â Â Â cpb_size = vbuf_size * 10;
>>>> +Â Â Â num_resources = 0;
>>>> +Â Â Â alloc_resource(&enc.fb, 4096, AMDGPU_GEM_DOMAIN_GTT);
>>>> +Â Â Â resources[num_resources++] = enc.fb.handle;
>>>> +Â Â Â alloc_resource(&enc.bs, bs_size, AMDGPU_GEM_DOMAIN_GTT);
>>>> +Â Â Â resources[num_resources++] = enc.bs.handle;
>>>> +Â Â Â alloc_resource(&enc.mvb, enc.mvbuf_size, AMDGPU_GEM_DOMAIN_GTT);
>>>> +Â Â Â resources[num_resources++] = enc.mvb.handle;
>>>> +Â Â Â alloc_resource(&enc.vbuf, vbuf_size, AMDGPU_GEM_DOMAIN_VRAM);
>>>> +Â Â Â resources[num_resources++] = enc.vbuf.handle;
>>>> +Â Â Â alloc_resource(&enc.mvrefbuf, vbuf_size, AMDGPU_GEM_DOMAIN_VRAM);
>>>> +Â Â Â resources[num_resources++] = enc.mvrefbuf.handle;
>>>> +Â Â Â alloc_resource(&enc.cpb, cpb_size, AMDGPU_GEM_DOMAIN_VRAM);
>>>> +Â Â Â resources[num_resources++] = enc.cpb.handle;
>>>> +Â Â Â resources[num_resources++] = ib_handle;
>>>> +
>>>> +Â Â Â r = amdgpu_bo_cpu_map(enc.vbuf.handle, (void **)&enc.vbuf.ptr);
>>>> +Â Â Â CU_ASSERT_EQUAL(r, 0);
>>>> +
>>>> +Â Â Â memset(enc.vbuf.ptr, 0, vbuf_size);
>>>> +Â Â Â for (i = 0; i < enc.height; ++i) {
>>>> +Â Â Â Â Â Â Â memcpy(enc.vbuf.ptr, (frame + i * enc.width), enc.width);
>>>> +Â Â Â Â Â Â Â enc.vbuf.ptr += ALIGN(enc.width, align);
>>>> +Â Â Â }
>>>> +Â Â Â for (i = 0; i < enc.height / 2; ++i) {
>>>> +Â Â Â Â Â Â Â memcpy(enc.vbuf.ptr, ((frame + enc.height * enc.width) + i
>>>> * enc.width), enc.width);
>>>> +Â Â Â Â Â Â Â enc.vbuf.ptr += ALIGN(enc.width, align);
>>>> +Â Â Â }
>>>> +
>>>> +Â Â Â r = amdgpu_bo_cpu_unmap(enc.vbuf.handle);
>>>> +Â Â Â CU_ASSERT_EQUAL(r, 0);
>>>> +
>>>> +Â Â Â r = amdgpu_bo_cpu_map(enc.mvrefbuf.handle, (void
>>>> **)&enc.mvrefbuf.ptr);
>>>> +Â Â Â CU_ASSERT_EQUAL(r, 0);
>>>> +
>>>> +Â Â Â memset(enc.mvrefbuf.ptr, 0, vbuf_size);
>>>> +Â Â Â for (i = 0; i < enc.height; ++i) {
>>>> +Â Â Â Â Â Â Â memcpy(enc.mvrefbuf.ptr, (frame + (enc.height - i -1) *
>>>> enc.width), enc.width);
>>>> +Â Â Â Â Â Â Â enc.mvrefbuf.ptr += ALIGN(enc.width, align);
>>>> +Â Â Â }
>>>> +Â Â Â for (i = 0; i < enc.height / 2; ++i) {
>>>> +Â Â Â Â Â Â Â memcpy(enc.mvrefbuf.ptr,
>>>> +Â Â Â Â Â Â Â ((frame + enc.height * enc.width) + (enc.height / 2 - i
>>>> -1) * enc.width), enc.width);
>>>> +Â Â Â Â Â Â Â enc.mvrefbuf.ptr += ALIGN(enc.width, align);
>>>> +Â Â Â }
>>>> +
>>>> +Â Â Â r = amdgpu_bo_cpu_unmap(enc.mvrefbuf.handle);
>>>> +Â Â Â CU_ASSERT_EQUAL(r, 0);
>>>> +
>>>> +Â Â Â amdgpu_cs_vce_config();
>>>> +
>>>> +Â Â Â vce_taskinfo[3] = 3;
>>>> +Â Â Â amdgpu_cs_vce_mv(&enc);
>>>> +Â Â Â check_mv_result(&enc);
>>>> +
>>>> +Â Â Â free_resource(&enc.fb);
>>>> +Â Â Â free_resource(&enc.bs);
>>>> +Â Â Â free_resource(&enc.vbuf);
>>>> +Â Â Â free_resource(&enc.cpb);
>>>> +Â Â Â free_resource(&enc.mvrefbuf);
>>>> +Â Â Â free_resource(&enc.mvb);
>>>> +}
>>>> +
>>>> +static void amdgpu_cs_vce_destroy(void)
>>>> +{
>>>> +Â Â Â int len, r;
>>>> +
>>>> +   num_resources = 0;
>>>> +Â Â Â alloc_resource(&enc.fb, 4096, AMDGPU_GEM_DOMAIN_GTT);
>>>> +Â Â Â resources[num_resources++] = enc.fb.handle;
>>>> +Â Â Â resources[num_resources++] = ib_handle;
>>>> +
>>>> +Â Â Â len = 0;
>>>> +Â Â Â memcpy(ib_cpu, vce_session, sizeof(vce_session));
>>>> +Â Â Â len += sizeof(vce_session) / 4;
>>>> +Â Â Â memcpy((ib_cpu + len), vce_taskinfo, sizeof(vce_taskinfo));
>>>> +Â Â Â ib_cpu[len + 3] = 1;
>>>> +Â Â Â len += sizeof(vce_taskinfo) / 4;
>>>> +Â Â Â memcpy((ib_cpu + len), vce_feedback, sizeof(vce_feedback));
>>>> +Â Â Â ib_cpu[len + 2] = enc.fb.addr >> 32;
>>>> +Â Â Â ib_cpu[len + 3] = enc.fb.addr;
>>>> +Â Â Â len += sizeof(vce_feedback) / 4;
>>>> +Â Â Â memcpy((ib_cpu + len), vce_destroy, sizeof(vce_destroy));
>>>> +Â Â Â len += sizeof(vce_destroy) / 4;
>>>> +
>>>> +Â Â Â r = submit(len, AMDGPU_HW_IP_VCE);
>>>> +Â Â Â CU_ASSERT_EQUAL(r, 0);
>>>> +
>>>> +Â Â Â free_resource(&enc.fb);
>>>> +}
>>>
>>
>
