Acked-by: Christian König <christian.koenig at amd.com> for the series as well.
But I think you should get Rex or somebody else who can confirm that
this is correct to take a look as well.
Christian.
Am 03.04.2018 um 04:46 schrieb zhoucm1:
> Acked-by: Chunming Zhou <david1.zhou at amd.com> for series.
>
>
> On 2018å¹´04æ??03æ?¥ 01:32, Alex Deucher wrote:
>> The calculation of the lane widths via
>> ATOM_PPLIB_PCIE_LINK_WIDTH_MASK and
>> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT macros did not increment the resulting
>> value, per the comment in pptable.h ("lanes - 1"), and per usage
>> elsewhere.
>> Port of the radeon fix to amdgpu.
>>
>> Bug: https://bugs.freedesktop.org/show_bug.cgi?id=102553
>> Signed-off-by: Alex Deucher <alexander.deucher at amd.com>
>> Cc: stable at vger.kernel.org
>> ---
>> Â drivers/gpu/drm/amd/amdgpu/si_dpm.c | 4 ++--
>> Â 1 file changed, 2 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/si_dpm.c
>> b/drivers/gpu/drm/amd/amdgpu/si_dpm.c
>> index 6253b272c944..b12d7c9d42a0 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/si_dpm.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/si_dpm.c
>> @@ -6372,9 +6372,9 @@ static void
>> si_set_pcie_lane_width_in_smc(struct amdgpu_device *adev,
>> Â {
>> Â Â Â Â Â u32 lane_width;
>> Â Â Â Â Â u32 new_lane_width =
>> -Â Â Â Â Â Â Â (amdgpu_new_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK)
>> >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT;
>> +Â Â Â Â Â Â Â ((amdgpu_new_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK)
>> >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1;
>> Â Â Â Â Â u32 current_lane_width =
>> -Â Â Â Â Â Â Â (amdgpu_current_state->caps &
>> ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT;
>> +Â Â Â Â Â Â Â ((amdgpu_current_state->caps &
>> ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT)
>> + 1;
>> Â Â Â Â Â Â if (new_lane_width != current_lane_width) {
>> Â Â Â Â Â Â Â Â Â amdgpu_set_pcie_lanes(adev, new_lane_width);
>
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