[PATCH 1/2] drm/amd/pp: Initialize default thermal control type for each asic

[Rex.Zhu@xxxxxxx (Rex Zhu)]

Signed-off-by: Rex Zhu <Rex.Zhu at amd.com>

Change-Id: I4e1b3f4bc66f28cc6a015182452d426ddd611224
---
 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c        | 9 +++++++++
 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 2 +-
 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h          | 1 +
 3 files changed, 11 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
index 6318438..3f1e822 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
@@ -33,6 +33,8 @@
 #include "ppsmc.h"
 #include "amd_acpi.h"
 #include "pp_psm.h"
+#include "atombios.h"
+#include "pptable.h"
 
 extern const struct pp_smumgr_func ci_smu_funcs;
 extern const struct pp_smumgr_func smu8_smu_funcs;
@@ -87,6 +89,7 @@ int hwmgr_early_init(struct pp_hwmgr *hwmgr)
 	hwmgr->fan_ctrl_is_in_default_mode = true;
 	hwmgr->reload_fw = 1;
 	hwmgr_init_workload_prority(hwmgr);
+	hwmgr->default_thermal_ctrl_type = ATOM_PP_THERMALCONTROLLER_NONE;
 
 	switch (hwmgr->chip_family) {
 	case AMDGPU_FAMILY_CI:
@@ -139,6 +142,7 @@ int hwmgr_early_init(struct pp_hwmgr *hwmgr)
 	case AMDGPU_FAMILY_AI:
 		switch (hwmgr->chip_id) {
 		case CHIP_VEGA10:
+			hwmgr->default_thermal_ctrl_type = ATOM_PP_THERMALCONTROLLER_VEGA10;
 			hwmgr->smumgr_funcs = &vega10_smu_funcs;
 			vega10_hwmgr_init(hwmgr);
 			break;
@@ -418,6 +422,7 @@ int polaris_set_asic_special_caps(struct pp_hwmgr *hwmgr)
 		phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 							PHM_PlatformCaps_TCPRamping);
 	}
+	hwmgr->default_thermal_ctrl_type = ATOM_PP_THERMALCONTROLLER_POLARIS10;
 	return 0;
 }
 
@@ -433,6 +438,7 @@ int fiji_set_asic_special_caps(struct pp_hwmgr *hwmgr)
 			PHM_PlatformCaps_TDRamping);
 	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 			PHM_PlatformCaps_TCPRamping);
+	hwmgr->default_thermal_ctrl_type = ATOM_PP_THERMALCONTROLLER_FIJI;
 	return 0;
 }
 
@@ -453,6 +459,7 @@ int tonga_set_asic_special_caps(struct pp_hwmgr *hwmgr)
 		      PHM_PlatformCaps_UVDPowerGating);
 	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 		      PHM_PlatformCaps_VCEPowerGating);
+	hwmgr->default_thermal_ctrl_type = ATOM_PP_THERMALCONTROLLER_TONGA;
 	return 0;
 }
 
@@ -468,6 +475,7 @@ int topaz_set_asic_special_caps(struct pp_hwmgr *hwmgr)
 			PHM_PlatformCaps_TDRamping);
 	phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 			PHM_PlatformCaps_TCPRamping);
+	hwmgr->default_thermal_ctrl_type = ATOM_PP_THERMALCONTROLLER_ICELAND;
 	return 0;
 }
 
@@ -485,5 +493,6 @@ int ci_set_asic_special_caps(struct pp_hwmgr *hwmgr)
 			PHM_PlatformCaps_MemorySpreadSpectrumSupport);
 	phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 			PHM_PlatformCaps_EngineSpreadSpectrumSupport);
+	hwmgr->default_thermal_ctrl_type = ATOM_PP_THERMALCONTROLLER_CISLANDS;
 	return 0;
 }
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
index 7bb9dd9..f177183 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
@@ -4830,7 +4830,7 @@ static int vega10_register_irq_handlers(struct pp_hwmgr *hwmgr)
 	source->funcs = &vega10_irq_funcs;
 
 	if (hwmgr->thermal_controller.ucType ==
-			ATOM_VEGA10_PP_THERMALCONTROLLER_VEGA10 ||
+			hwmgr->default_thermal_ctrl_type ||
 		hwmgr->thermal_controller.ucType ==
 			ATOM_VEGA10_PP_THERMALCONTROLLER_EMC2103_WITH_INTERNAL) {
 
diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
index efdcf31..f32d5db 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h
@@ -720,6 +720,7 @@ struct pp_hwmgr {
 	uint32_t usec_timeout;
 	void *pptable;
 	struct phm_platform_descriptor platform_descriptor;
+	uint8_t default_thermal_ctrl_type;
 	void *backend;
 
 	void *smu_backend;
-- 
1.9.1