On Mon, Mar 19, 2018 at 5:32 AM, Hawking Zhang <Hawking.Zhang at amd.com> wrote:
> PCIE_INDEX2/DATA2 pair will be used for smn register accessing since from vega.
> PCIE_INDEX/DATA pair should be reserved for smu
>
> Change-Id: Ie597d89001e706225521c94161d2b40443ec3c48
> Signed-off-by: Hawking Zhang <Hawking.Zhang at amd.com>
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
> index 1cf3424..6f9c549 100644
> --- a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
> +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
> @@ -220,12 +220,12 @@ static u32 nbio_v6_1_get_hdp_flush_done_offset(struct amdgpu_device *adev)
>
> static u32 nbio_v6_1_get_pcie_index_offset(struct amdgpu_device *adev)
> {
> - return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_INDEX);
> + return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_INDEX2);
> }
>
> static u32 nbio_v6_1_get_pcie_data_offset(struct amdgpu_device *adev)
> {
> - return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_DATA);
> + return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_DATA2);
> }
>
> static const struct nbio_hdp_flush_reg nbio_v6_1_hdp_flush_reg = {
> --
> 2.7.4
>
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