[PATCH] drm/amd/pp: Fix memory leak in error path in smumgr

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Free the backend structure if we fail to allocate device memory.

Change-Id: Ib5fbd507369575b90df57a55d3e7318c769b3e27
Signed-off-by: Rex Zhu <Rex.Zhu at amd.com>
---
 drivers/gpu/drm/amd/powerplay/smumgr/cz_smumgr.c   | 35 +++++++++++++---------
 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c |  8 +++--
 .../gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c  |  8 +++--
 .../drm/amd/powerplay/smumgr/polaris10_smumgr.c    |  8 +++--
 drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.c   | 21 ++++++++-----
 .../gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c    |  8 +++--
 6 files changed, 54 insertions(+), 34 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/cz_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/cz_smumgr.c
index 957739a..ee8968c 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/cz_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/cz_smumgr.c
@@ -746,8 +746,6 @@ static int cz_smu_init(struct pp_hwmgr *hwmgr)
 	if (cz_smu == NULL)
 		return -ENOMEM;
 
-	hwmgr->smu_backend = cz_smu;
-
 	cz_smu->toc_buffer.data_size = 4096;
 	cz_smu->smu_buffer.data_size =
 		ALIGN(UCODE_ID_RLC_SCRATCH_SIZE_BYTE, 32) +
@@ -764,7 +762,7 @@ static int cz_smu_init(struct pp_hwmgr *hwmgr)
 				&cz_smu->toc_buffer.mc_addr,
 				&cz_smu->toc_buffer.kaddr);
 	if (ret)
-		return -EINVAL;
+		goto err2;
 
 	ret = amdgpu_bo_create_kernel((struct amdgpu_device *)hwmgr->adev,
 				cz_smu->smu_buffer.data_size,
@@ -773,19 +771,15 @@ static int cz_smu_init(struct pp_hwmgr *hwmgr)
 				&cz_smu->smu_buffer.handle,
 				&cz_smu->smu_buffer.mc_addr,
 				&cz_smu->smu_buffer.kaddr);
-	if (ret) {
-		amdgpu_bo_free_kernel(&cz_smu->toc_buffer.handle,
-					&cz_smu->toc_buffer.mc_addr,
-					&cz_smu->toc_buffer.kaddr);
-		return -EINVAL;
-	}
+	if (ret)
+		goto err1;
 
 	if (0 != cz_smu_populate_single_scratch_entry(hwmgr,
 		CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SCRATCH,
 		UCODE_ID_RLC_SCRATCH_SIZE_BYTE,
 		&cz_smu->scratch_buffer[cz_smu->scratch_buffer_length++])) {
 		pr_err("Error when Populate Firmware Entry.\n");
-		return -1;
+		goto err0;
 	}
 
 	if (0 != cz_smu_populate_single_scratch_entry(hwmgr,
@@ -793,14 +787,14 @@ static int cz_smu_init(struct pp_hwmgr *hwmgr)
 		UCODE_ID_RLC_SRM_ARAM_SIZE_BYTE,
 		&cz_smu->scratch_buffer[cz_smu->scratch_buffer_length++])) {
 		pr_err("Error when Populate Firmware Entry.\n");
-		return -1;
+		goto err0;
 	}
 	if (0 != cz_smu_populate_single_scratch_entry(hwmgr,
 		CZ_SCRATCH_ENTRY_UCODE_ID_RLC_SRM_DRAM,
 		UCODE_ID_RLC_SRM_DRAM_SIZE_BYTE,
 		&cz_smu->scratch_buffer[cz_smu->scratch_buffer_length++])) {
 		pr_err("Error when Populate Firmware Entry.\n");
-		return -1;
+		goto err0;
 	}
 
 	if (0 != cz_smu_populate_single_scratch_entry(hwmgr,
@@ -808,7 +802,7 @@ static int cz_smu_init(struct pp_hwmgr *hwmgr)
 		sizeof(struct SMU8_MultimediaPowerLogData),
 		&cz_smu->scratch_buffer[cz_smu->scratch_buffer_length++])) {
 		pr_err("Error when Populate Firmware Entry.\n");
-		return -1;
+		goto err0;
 	}
 
 	if (0 != cz_smu_populate_single_scratch_entry(hwmgr,
@@ -816,10 +810,23 @@ static int cz_smu_init(struct pp_hwmgr *hwmgr)
 		sizeof(struct SMU8_Fusion_ClkTable),
 		&cz_smu->scratch_buffer[cz_smu->scratch_buffer_length++])) {
 		pr_err("Error when Populate Firmware Entry.\n");
-		return -1;
+		goto err0;
 	}
 
+	hwmgr->smu_backend = cz_smu;
 	return 0;
+
+err0:
+	amdgpu_bo_free_kernel(&cz_smu->smu_buffer.handle,
+				&cz_smu->smu_buffer.mc_addr,
+				&cz_smu->smu_buffer.kaddr);
+err1:
+	amdgpu_bo_free_kernel(&cz_smu->toc_buffer.handle,
+				&cz_smu->toc_buffer.mc_addr,
+				&cz_smu->toc_buffer.kaddr);
+err2:
+	kfree(cz_smu);
+	return -EINVAL;
 }
 
 static int cz_smu_fini(struct pp_hwmgr *hwmgr)
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
index ed2e2e9..ff9ba9d 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c
@@ -352,10 +352,12 @@ static int fiji_smu_init(struct pp_hwmgr *hwmgr)
 	if (fiji_priv == NULL)
 		return -ENOMEM;
 
-	hwmgr->smu_backend = fiji_priv;
-
-	if (smu7_init(hwmgr))
+	if (smu7_init(hwmgr)) {
+		kfree(fiji_priv);
 		return -EINVAL;
+	}
+
+	hwmgr->smu_backend = fiji_priv;
 
 	return 0;
 }
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c
index 6255edf..91ab7c8 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c
@@ -269,10 +269,12 @@ static int iceland_smu_init(struct pp_hwmgr *hwmgr)
 	if (iceland_priv == NULL)
 		return -ENOMEM;
 
-	hwmgr->smu_backend = iceland_priv;
-
-	if (smu7_init(hwmgr))
+	if (smu7_init(hwmgr)) {
+		kfree(iceland_priv);
 		return -EINVAL;
+	}
+
+	hwmgr->smu_backend = iceland_priv;
 
 	return 0;
 }
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
index 0609acf..03b95b4 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c
@@ -347,10 +347,12 @@ static int polaris10_smu_init(struct pp_hwmgr *hwmgr)
 	if (smu_data == NULL)
 		return -ENOMEM;
 
-	hwmgr->smu_backend = smu_data;
-
-	if (smu7_init(hwmgr))
+	if (smu7_init(hwmgr)) {
+		kfree(smu_data);
 		return -EINVAL;
+	}
+
+	hwmgr->smu_backend = smu_data;
 
 	return 0;
 }
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.c
index e2ee23a..ad2fa0d 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.c
@@ -338,7 +338,6 @@ static int rv_smu_init(struct pp_hwmgr *hwmgr)
 	if (!priv)
 		return -ENOMEM;
 
-	hwmgr->smu_backend = priv;
 
 	/* allocate space for watermarks table */
 	r = amdgpu_bo_create_kernel((struct amdgpu_device *)hwmgr->adev,
@@ -350,7 +349,7 @@ static int rv_smu_init(struct pp_hwmgr *hwmgr)
 			&kaddr);
 
 	if (r)
-		return -EINVAL;
+		goto err0;
 
 	priv->smu_tables.entry[WMTABLE].version = 0x01;
 	priv->smu_tables.entry[WMTABLE].size = sizeof(Watermarks_t);
@@ -368,12 +367,8 @@ static int rv_smu_init(struct pp_hwmgr *hwmgr)
 			&mc_addr,
 			&kaddr);
 
-	if (r) {
-		amdgpu_bo_free_kernel(&priv->smu_tables.entry[WMTABLE].handle,
-					&priv->smu_tables.entry[WMTABLE].mc_addr,
-					&priv->smu_tables.entry[WMTABLE].table);
-		return -EINVAL;
-	}
+	if (r)
+		goto err1;
 
 	priv->smu_tables.entry[CLOCKTABLE].version = 0x01;
 	priv->smu_tables.entry[CLOCKTABLE].size = sizeof(DpmClocks_t);
@@ -382,7 +377,17 @@ static int rv_smu_init(struct pp_hwmgr *hwmgr)
 	priv->smu_tables.entry[CLOCKTABLE].table = kaddr;
 	priv->smu_tables.entry[CLOCKTABLE].handle = handle;
 
+	hwmgr->smu_backend = priv;
+
 	return 0;
+
+err1:
+	amdgpu_bo_free_kernel(&priv->smu_tables.entry[WMTABLE].handle,
+				&priv->smu_tables.entry[WMTABLE].mc_addr,
+				&priv->smu_tables.entry[WMTABLE].table);
+err0:
+	kfree(priv);
+	return -EINVAL;
 }
 
 const struct pp_smumgr_func rv_smu_funcs = {
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c
index 39d6f4e..f29d10c 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c
@@ -227,10 +227,12 @@ static int tonga_smu_init(struct pp_hwmgr *hwmgr)
 	if (tonga_priv == NULL)
 		return -ENOMEM;
 
-	hwmgr->smu_backend = tonga_priv;
-
-	if (smu7_init(hwmgr))
+	if (smu7_init(hwmgr)) {
+		kfree(tonga_priv);
 		return -EINVAL;
+	}
+
+	hwmgr->smu_backend = tonga_priv;
 
 	return 0;
 }
-- 
1.9.1



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