[PATCH libdrm] Revert "tests/amdgpu: add bo eviction test"

christian.koenig@xxxxxxx (Christian König) · Thu, 1 Mar 2018 10:52:43 +0100

Andrey worked on this, he should know that of hand.

Christian.

Am 01.03.2018 um 10:43 schrieb zhoucm1:
>
>
> On 2018å¹´03æ??01æ?¥ 17:40, Christian KÃ¶nig wrote:
>> Am 01.03.2018 um 10:37 schrieb Chunming Zhou:
>>> if some system hase no swap space and memory is less, than the test
>>> could fail.
>>> And bo eviction test takes much more time in some system, which effects
>>> automation test result and efficiency.
>>> So revert it now, only can be used by developer manually.
>>
>> In this case I would rather disable it by default.
> Could I ask how to disable it by default?
>
> Thanks,
> David Zhou
>>
>> But I think that this is a rather valid test and should work even 
>> under low memory conditions.
>>
>> Christian.
>>
>>>
>>> This reverts commit 09642c073e8af71127cf98b48fe1b2a376c606cf.
>>> ---
>>> Â  tests/amdgpu/amdgpu_test.h |Â  23 -------
>>> Â  tests/amdgpu/basic_tests.c | 160 
>>> +--------------------------------------------
>>> Â  2 files changed, 1 insertion(+), 182 deletions(-)
>>>
>>> diff --git a/tests/amdgpu/amdgpu_test.h b/tests/amdgpu/amdgpu_test.h
>>> index 7397dea0..1db803c6 100644
>>> --- a/tests/amdgpu/amdgpu_test.h
>>> +++ b/tests/amdgpu/amdgpu_test.h
>>> @@ -251,29 +251,6 @@ static inline int gpu_mem_free(amdgpu_bo_handle 
>>> bo,
>>> Â Â Â Â Â  return 0;
>>> Â  }
>>> Â  -static inline int
>>> -amdgpu_bo_alloc_wrap(amdgpu_device_handle dev, unsigned size,
>>> -Â Â Â Â Â Â Â Â Â Â Â Â  unsigned alignment, unsigned heap, uint64_t flags,
>>> -Â Â Â Â Â Â Â Â Â Â Â Â  amdgpu_bo_handle *bo)
>>> -{
>>> -Â Â Â  struct amdgpu_bo_alloc_request request = {};
>>> -Â Â Â  amdgpu_bo_handle buf_handle;
>>> -Â Â Â  int r;
>>> -
>>> -Â Â Â  request.alloc_size = size;
>>> -Â Â Â  request.phys_alignment = alignment;
>>> -Â Â Â  request.preferred_heap = heap;
>>> -Â Â Â  request.flags = flags;
>>> -
>>> -Â Â Â  r = amdgpu_bo_alloc(dev, &request, &buf_handle);
>>> -Â Â Â  if (r)
>>> -Â Â Â Â Â Â Â  return r;
>>> -
>>> -Â Â Â  *bo = buf_handle;
>>> -
>>> -Â Â Â  return 0;
>>> -}
>>> -
>>> Â  static inline int
>>> Â  amdgpu_bo_alloc_and_map(amdgpu_device_handle dev, unsigned size,
>>> Â Â Â Â Â Â Â Â Â Â Â Â Â  unsigned alignment, unsigned heap, uint64_t flags,
>>> diff --git a/tests/amdgpu/basic_tests.c b/tests/amdgpu/basic_tests.c
>>> index 0ea010a8..354b0157 100644
>>> --- a/tests/amdgpu/basic_tests.c
>>> +++ b/tests/amdgpu/basic_tests.c
>>> @@ -51,22 +51,14 @@ static void amdgpu_command_submission_sdma(void);
>>> Â  static void amdgpu_userptr_test(void);
>>> Â  static void amdgpu_semaphore_test(void);
>>> Â  static void amdgpu_sync_dependency_test(void);
>>> -static void amdgpu_bo_eviction_test(void);
>>> Â  Â  static void 
>>> amdgpu_command_submission_write_linear_helper(unsigned ip_type);
>>> Â  static void amdgpu_command_submission_const_fill_helper(unsigned 
>>> ip_type);
>>> Â  static void amdgpu_command_submission_copy_linear_helper(unsigned 
>>> ip_type);
>>> -static void amdgpu_test_exec_cs_helper(amdgpu_context_handle 
>>> context_handle,
>>> -Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â  unsigned ip_type,
>>> -Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â  int instance, int pm4_dw, uint32_t *pm4_src,
>>> -Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â  int res_cnt, amdgpu_bo_handle *resources,
>>> -Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â  struct amdgpu_cs_ib_info *ib_info,
>>> -Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â  struct amdgpu_cs_request *ibs_request);
>>> -
>>> +
>>> Â  CU_TestInfo basic_tests[] = {
>>> Â Â Â Â Â  { "Query Info Test",Â  amdgpu_query_info_test },
>>> Â Â Â Â Â  { "Userptr Test",Â  amdgpu_userptr_test },
>>> -Â Â Â  { "bo eviction Test",Â  amdgpu_bo_eviction_test },
>>> Â Â Â Â Â  { "Command submission Test (GFX)", 
>>> amdgpu_command_submission_gfx },
>>> Â Â Â Â Â  { "Command submission Test (Compute)", 
>>> amdgpu_command_submission_compute },
>>> Â Â Â Â Â  { "Command submission Test (Multi-Fence)", 
>>> amdgpu_command_submission_multi_fence },
>>> @@ -524,156 +516,6 @@ static void 
>>> amdgpu_command_submission_gfx_cp_copy_data(void)
>>> amdgpu_command_submission_copy_linear_helper(AMDGPU_HW_IP_GFX);
>>> Â  }
>>> Â  -static void amdgpu_bo_eviction_test(void)
>>> -{
>>> -Â Â Â  const int sdma_write_length = 1024;
>>> -Â Â Â  const int pm4_dw = 256;
>>> -Â Â Â  amdgpu_context_handle context_handle;
>>> -Â Â Â  amdgpu_bo_handle bo1, bo2, vram_max[2], gtt_max[2];
>>> -Â Â Â  amdgpu_bo_handle *resources;
>>> -Â Â Â  uint32_t *pm4;
>>> -Â Â Â  struct amdgpu_cs_ib_info *ib_info;
>>> -Â Â Â  struct amdgpu_cs_request *ibs_request;
>>> -Â Â Â  uint64_t bo1_mc, bo2_mc;
>>> -Â Â Â  volatile unsigned char *bo1_cpu, *bo2_cpu;
>>> -Â Â Â  int i, j, r, loop1, loop2;
>>> -Â Â Â  uint64_t gtt_flags[2] = {0, AMDGPU_GEM_CREATE_CPU_GTT_USWC};
>>> -Â Â Â  amdgpu_va_handle bo1_va_handle, bo2_va_handle;
>>> -Â Â Â  struct amdgpu_heap_info vram_info, gtt_info;
>>> -
>>> -Â Â Â  pm4 = calloc(pm4_dw, sizeof(*pm4));
>>> -Â Â Â  CU_ASSERT_NOT_EQUAL(pm4, NULL);
>>> -
>>> -Â Â Â  ib_info = calloc(1, sizeof(*ib_info));
>>> -Â Â Â  CU_ASSERT_NOT_EQUAL(ib_info, NULL);
>>> -
>>> -Â Â Â  ibs_request = calloc(1, sizeof(*ibs_request));
>>> -Â Â Â  CU_ASSERT_NOT_EQUAL(ibs_request, NULL);
>>> -
>>> -Â Â Â  r = amdgpu_cs_ctx_create(device_handle, &context_handle);
>>> -Â Â Â  CU_ASSERT_EQUAL(r, 0);
>>> -
>>> -Â Â Â  /* prepare resource */
>>> -Â Â Â  resources = calloc(4, sizeof(amdgpu_bo_handle));
>>> -Â Â Â  CU_ASSERT_NOT_EQUAL(resources, NULL);
>>> -
>>> -Â Â Â  r = amdgpu_query_heap_info(device_handle, AMDGPU_GEM_DOMAIN_VRAM,
>>> -Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â  0, &vram_info);
>>> -Â Â Â  CU_ASSERT_EQUAL(r, 0);
>>> -
>>> -Â Â Â  r = amdgpu_bo_alloc_wrap(device_handle, 
>>> vram_info.max_allocation, 4096,
>>> -Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â  AMDGPU_GEM_DOMAIN_VRAM, 0, &vram_max[0]);
>>> -Â Â Â  CU_ASSERT_EQUAL(r, 0);
>>> -Â Â Â  r = amdgpu_bo_alloc_wrap(device_handle, 
>>> vram_info.max_allocation, 4096,
>>> -Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â  AMDGPU_GEM_DOMAIN_VRAM, 0, &vram_max[1]);
>>> -Â Â Â  CU_ASSERT_EQUAL(r, 0);
>>> -
>>> -Â Â Â  r = amdgpu_query_heap_info(device_handle, AMDGPU_GEM_DOMAIN_GTT,
>>> -Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â  0, &gtt_info);
>>> -Â Â Â  CU_ASSERT_EQUAL(r, 0);
>>> -
>>> -Â Â Â  r = amdgpu_bo_alloc_wrap(device_handle, 
>>> gtt_info.max_allocation, 4096,
>>> -Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â  AMDGPU_GEM_DOMAIN_GTT, 0, &gtt_max[0]);
>>> -Â Â Â  CU_ASSERT_EQUAL(r, 0);
>>> -Â Â Â  r = amdgpu_bo_alloc_wrap(device_handle, 
>>> gtt_info.max_allocation, 4096,
>>> -Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â  AMDGPU_GEM_DOMAIN_GTT, 0, &gtt_max[1]);
>>> -Â Â Â  CU_ASSERT_EQUAL(r, 0);
>>> -
>>> -
>>> -
>>> -Â Â Â  loop1 = loop2 = 0;
>>> -Â Â Â  /* run 9 circle to test all mapping combination */
>>> -Â Â Â  while(loop1 < 2) {
>>> -Â Â Â Â Â Â Â  while(loop2 < 2) {
>>> -Â Â Â Â Â Â Â Â Â Â Â  /* allocate UC bo1for sDMA use */
>>> -Â Â Â Â Â Â Â Â Â Â Â  r = amdgpu_bo_alloc_and_map(device_handle,
>>> -Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â  sdma_write_length, 4096,
>>> -Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â  AMDGPU_GEM_DOMAIN_GTT,
>>> -Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â  gtt_flags[loop1], &bo1,
>>> -Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â  (void**)&bo1_cpu, &bo1_mc,
>>> -Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â  &bo1_va_handle);
>>> -Â Â Â Â Â Â Â Â Â Â Â  CU_ASSERT_EQUAL(r, 0);
>>> -
>>> -Â Â Â Â Â Â Â Â Â Â Â  /* set bo1 */
>>> -Â Â Â Â Â Â Â Â Â Â Â  memset((void*)bo1_cpu, 0xaa, sdma_write_length);
>>> -
>>> -Â Â Â Â Â Â Â Â Â Â Â  /* allocate UC bo2 for sDMA use */
>>> -Â Â Â Â Â Â Â Â Â Â Â  r = amdgpu_bo_alloc_and_map(device_handle,
>>> -Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â  sdma_write_length, 4096,
>>> -Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â  AMDGPU_GEM_DOMAIN_GTT,
>>> -Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â  gtt_flags[loop2], &bo2,
>>> -Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â  (void**)&bo2_cpu, &bo2_mc,
>>> -Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â  &bo2_va_handle);
>>> -Â Â Â Â Â Â Â Â Â Â Â  CU_ASSERT_EQUAL(r, 0);
>>> -
>>> -Â Â Â Â Â Â Â Â Â Â Â  /* clear bo2 */
>>> -Â Â Â Â Â Â Â Â Â Â Â  memset((void*)bo2_cpu, 0, sdma_write_length);
>>> -
>>> -Â Â Â Â Â Â Â Â Â Â Â  resources[0] = bo1;
>>> -Â Â Â Â Â Â Â Â Â Â Â  resources[1] = bo2;
>>> -Â Â Â Â Â Â Â Â Â Â Â  resources[2] = vram_max[loop2];
>>> -Â Â Â Â Â Â Â Â Â Â Â  resources[3] = gtt_max[loop2];
>>> -
>>> -Â Â Â Â Â Â Â Â Â Â Â  /* fulfill PM4: test DMA copy linear */
>>> -Â Â Â Â Â Â Â Â Â Â Â  i = j = 0;
>>> -Â Â Â Â Â Â Â Â Â Â Â  if (family_id == AMDGPU_FAMILY_SI) {
>>> -Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â  pm4[i++] = SDMA_PACKET_SI(SDMA_OPCODE_COPY_SI, 0, 
>>> 0, 0,
>>> -Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â  sdma_write_length);
>>> -Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â  pm4[i++] = 0xffffffff & bo2_mc;
>>> -Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â  pm4[i++] = 0xffffffff & bo1_mc;
>>> -Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â  pm4[i++] = (0xffffffff00000000 & bo2_mc) >> 32;
>>> -Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â  pm4[i++] = (0xffffffff00000000 & bo1_mc) >> 32;
>>> -Â Â Â Â Â Â Â Â Â Â Â  } else {
>>> -Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â  pm4[i++] = SDMA_PACKET(SDMA_OPCODE_COPY, 
>>> SDMA_COPY_SUB_OPCODE_LINEAR, 0);
>>> -Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â  if (family_id >= AMDGPU_FAMILY_AI)
>>> -Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â  pm4[i++] = sdma_write_length - 1;
>>> -Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â  else
>>> -Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â  pm4[i++] = sdma_write_length;
>>> -Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â  pm4[i++] = 0;
>>> -Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â  pm4[i++] = 0xffffffff & bo1_mc;
>>> -Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â  pm4[i++] = (0xffffffff00000000 & bo1_mc) >> 32;
>>> -Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â  pm4[i++] = 0xffffffff & bo2_mc;
>>> -Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â  pm4[i++] = (0xffffffff00000000 & bo2_mc) >> 32;
>>> -Â Â Â Â Â Â Â Â Â Â Â  }
>>> -
>>> -Â Â Â Â Â Â Â Â Â Â Â  amdgpu_test_exec_cs_helper(context_handle,
>>> -Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â  AMDGPU_HW_IP_DMA, 0,
>>> -Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â  i, pm4,
>>> -Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â  4, resources,
>>> -Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â  ib_info, ibs_request);
>>> -
>>> -Â Â Â Â Â Â Â Â Â Â Â  /* verify if SDMA test result meets with expected */
>>> -Â Â Â Â Â Â Â Â Â Â Â  i = 0;
>>> -Â Â Â Â Â Â Â Â Â Â Â  while(i < sdma_write_length) {
>>> -Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â  CU_ASSERT_EQUAL(bo2_cpu[i++], 0xaa);
>>> -Â Â Â Â Â Â Â Â Â Â Â  }
>>> -Â Â Â Â Â Â Â Â Â Â Â  r = amdgpu_bo_unmap_and_free(bo1, bo1_va_handle, bo1_mc,
>>> -Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â  sdma_write_length);
>>> -Â Â Â Â Â Â Â Â Â Â Â  CU_ASSERT_EQUAL(r, 0);
>>> -Â Â Â Â Â Â Â Â Â Â Â  r = amdgpu_bo_unmap_and_free(bo2, bo2_va_handle, bo2_mc,
>>> -Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â  sdma_write_length);
>>> -Â Â Â Â Â Â Â Â Â Â Â  CU_ASSERT_EQUAL(r, 0);
>>> -Â Â Â Â Â Â Â Â Â Â Â  loop2++;
>>> -Â Â Â Â Â Â Â  }
>>> -Â Â Â Â Â Â Â  loop2 = 0;
>>> -Â Â Â Â Â Â Â  loop1++;
>>> -Â Â Â  }
>>> -Â Â Â  amdgpu_bo_free(vram_max[0]);
>>> -Â Â Â  amdgpu_bo_free(vram_max[1]);
>>> -Â Â Â  amdgpu_bo_free(gtt_max[0]);
>>> -Â Â Â  amdgpu_bo_free(gtt_max[1]);
>>> -Â Â Â  /* clean resources */
>>> -Â Â Â  free(resources);
>>> -Â Â Â  free(ibs_request);
>>> -Â Â Â  free(ib_info);
>>> -Â Â Â  free(pm4);
>>> -
>>> -Â Â Â  /* end of test */
>>> -Â Â Â  r = amdgpu_cs_ctx_free(context_handle);
>>> -Â Â Â  CU_ASSERT_EQUAL(r, 0);
>>> -}
>>> -
>>> -
>>> Â  static void amdgpu_command_submission_gfx(void)
>>> Â  {
>>> Â Â Â Â Â  /* write data using the CP */
>>
>