Am 01.03.2018 um 03:04 schrieb Alex Deucher: > Rather than querying it every time we need it. > Also fixes a crash in VM pass through if there is no > root bridge because the cached value fetch already checks > this properly. > > v2: fix includes > > Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=105244 > Signed-off-by: Alex Deucher <alexander.deucher at amd.com> Acked-by: Christian König <christian.koenig at amd.com> > Cc: stable at vger.kernel.org > --- > drivers/gpu/drm/amd/amdgpu/si.c | 22 ++++++++-------- > drivers/gpu/drm/amd/amdgpu/si_dpm.c | 50 ++++++++++--------------------------- > 2 files changed, 23 insertions(+), 49 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/si.c b/drivers/gpu/drm/amd/amdgpu/si.c > index f20c4b7414e8..6e61b56bfbfc 100644 > --- a/drivers/gpu/drm/amd/amdgpu/si.c > +++ b/drivers/gpu/drm/amd/amdgpu/si.c > @@ -31,6 +31,7 @@ > #include "amdgpu_uvd.h" > #include "amdgpu_vce.h" > #include "atom.h" > +#include "amd_pcie.h" > #include "amdgpu_powerplay.h" > #include "sid.h" > #include "si_ih.h" > @@ -1484,8 +1485,8 @@ static void si_pcie_gen3_enable(struct amdgpu_device *adev) > { > struct pci_dev *root = adev->pdev->bus->self; > int bridge_pos, gpu_pos; > - u32 speed_cntl, mask, current_data_rate; > - int ret, i; > + u32 speed_cntl, current_data_rate; > + int i; > u16 tmp16; > > if (pci_is_root_bus(adev->pdev->bus)) > @@ -1497,23 +1498,20 @@ static void si_pcie_gen3_enable(struct amdgpu_device *adev) > if (adev->flags & AMD_IS_APU) > return; > > - ret = drm_pcie_get_speed_cap_mask(adev->ddev, &mask); > - if (ret != 0) > - return; > - > - if (!(mask & (DRM_PCIE_SPEED_50 | DRM_PCIE_SPEED_80))) > + if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 | > + CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3))) > return; > > speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); > current_data_rate = (speed_cntl & LC_CURRENT_DATA_RATE_MASK) >> > LC_CURRENT_DATA_RATE_SHIFT; > - if (mask & DRM_PCIE_SPEED_80) { > + if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) { > if (current_data_rate == 2) { > DRM_INFO("PCIE gen 3 link speeds already enabled\n"); > return; > } > DRM_INFO("enabling PCIE gen 3 link speeds, disable with amdgpu.pcie_gen2=0\n"); > - } else if (mask & DRM_PCIE_SPEED_50) { > + } else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2) { > if (current_data_rate == 1) { > DRM_INFO("PCIE gen 2 link speeds already enabled\n"); > return; > @@ -1529,7 +1527,7 @@ static void si_pcie_gen3_enable(struct amdgpu_device *adev) > if (!gpu_pos) > return; > > - if (mask & DRM_PCIE_SPEED_80) { > + if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) { > if (current_data_rate != 2) { > u16 bridge_cfg, gpu_cfg; > u16 bridge_cfg2, gpu_cfg2; > @@ -1612,9 +1610,9 @@ static void si_pcie_gen3_enable(struct amdgpu_device *adev) > > pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16); > tmp16 &= ~0xf; > - if (mask & DRM_PCIE_SPEED_80) > + if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) > tmp16 |= 3; > - else if (mask & DRM_PCIE_SPEED_50) > + else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2) > tmp16 |= 2; > else > tmp16 |= 1; > diff --git a/drivers/gpu/drm/amd/amdgpu/si_dpm.c b/drivers/gpu/drm/amd/amdgpu/si_dpm.c > index 8138053fcef1..8137c02fd16a 100644 > --- a/drivers/gpu/drm/amd/amdgpu/si_dpm.c > +++ b/drivers/gpu/drm/amd/amdgpu/si_dpm.c > @@ -26,6 +26,7 @@ > #include "amdgpu_pm.h" > #include "amdgpu_dpm.h" > #include "amdgpu_atombios.h" > +#include "amd_pcie.h" > #include "sid.h" > #include "r600_dpm.h" > #include "si_dpm.h" > @@ -3331,29 +3332,6 @@ static void btc_apply_voltage_delta_rules(struct amdgpu_device *adev, > } > } > > -static enum amdgpu_pcie_gen r600_get_pcie_gen_support(struct amdgpu_device *adev, > - u32 sys_mask, > - enum amdgpu_pcie_gen asic_gen, > - enum amdgpu_pcie_gen default_gen) > -{ > - switch (asic_gen) { > - case AMDGPU_PCIE_GEN1: > - return AMDGPU_PCIE_GEN1; > - case AMDGPU_PCIE_GEN2: > - return AMDGPU_PCIE_GEN2; > - case AMDGPU_PCIE_GEN3: > - return AMDGPU_PCIE_GEN3; > - default: > - if ((sys_mask & DRM_PCIE_SPEED_80) && (default_gen == AMDGPU_PCIE_GEN3)) > - return AMDGPU_PCIE_GEN3; > - else if ((sys_mask & DRM_PCIE_SPEED_50) && (default_gen == AMDGPU_PCIE_GEN2)) > - return AMDGPU_PCIE_GEN2; > - else > - return AMDGPU_PCIE_GEN1; > - } > - return AMDGPU_PCIE_GEN1; > -} > - > static void r600_calculate_u_and_p(u32 i, u32 r_c, u32 p_b, > u32 *p, u32 *u) > { > @@ -5028,10 +5006,11 @@ static int si_populate_smc_acpi_state(struct amdgpu_device *adev, > table->ACPIState.levels[0].vddc.index, > &table->ACPIState.levels[0].std_vddc); > } > - table->ACPIState.levels[0].gen2PCIE = (u8)r600_get_pcie_gen_support(adev, > - si_pi->sys_pcie_mask, > - si_pi->boot_pcie_gen, > - AMDGPU_PCIE_GEN1); > + table->ACPIState.levels[0].gen2PCIE = > + (u8)amdgpu_get_pcie_gen_support(adev, > + si_pi->sys_pcie_mask, > + si_pi->boot_pcie_gen, > + AMDGPU_PCIE_GEN1); > > if (si_pi->vddc_phase_shed_control) > si_populate_phase_shedding_value(adev, > @@ -7168,10 +7147,10 @@ static void si_parse_pplib_clock_info(struct amdgpu_device *adev, > pl->vddc = le16_to_cpu(clock_info->si.usVDDC); > pl->vddci = le16_to_cpu(clock_info->si.usVDDCI); > pl->flags = le32_to_cpu(clock_info->si.ulFlags); > - pl->pcie_gen = r600_get_pcie_gen_support(adev, > - si_pi->sys_pcie_mask, > - si_pi->boot_pcie_gen, > - clock_info->si.ucPCIEGen); > + pl->pcie_gen = amdgpu_get_pcie_gen_support(adev, > + si_pi->sys_pcie_mask, > + si_pi->boot_pcie_gen, > + clock_info->si.ucPCIEGen); > > /* patch up vddc if necessary */ > ret = si_get_leakage_voltage_from_leakage_index(adev, pl->vddc, > @@ -7326,7 +7305,6 @@ static int si_dpm_init(struct amdgpu_device *adev) > struct si_power_info *si_pi; > struct atom_clock_dividers dividers; > int ret; > - u32 mask; > > si_pi = kzalloc(sizeof(struct si_power_info), GFP_KERNEL); > if (si_pi == NULL) > @@ -7336,11 +7314,9 @@ static int si_dpm_init(struct amdgpu_device *adev) > eg_pi = &ni_pi->eg; > pi = &eg_pi->rv7xx; > > - ret = drm_pcie_get_speed_cap_mask(adev->ddev, &mask); > - if (ret) > - si_pi->sys_pcie_mask = 0; > - else > - si_pi->sys_pcie_mask = mask; > + si_pi->sys_pcie_mask = > + (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_MASK) >> > + CAIL_PCIE_LINK_SPEED_SUPPORT_SHIFT; > si_pi->force_pcie_gen = AMDGPU_PCIE_GEN_INVALID; > si_pi->boot_pcie_gen = si_get_current_pcie_speed(adev); >
