Oh, wait a second this is for the encode ring, isn't it? I only fixed
the decode ring.
In this case the patch is Reviewed-by: Christian König
<christian.koenig at amd.com>
Regards,
Christian.
Am 27.02.2018 um 16:13 schrieb Christian König:
> You are using outdated code, that has already be fixed on
> amd-staging-drm-next.
>
> Christian.
>
> Am 27.02.2018 um 16:06 schrieb James Zhu:
>> Emit frame size should match with corresponding function,
>> uvd_v6_0_enc_ring_emit_vm_flush has 5 amdgpu_ring_write
>>
>> Signed-off-by: James Zhu <James.Zhu at amd.com>
>> ---
>> Â drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 2 +-
>> Â 1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
>> b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
>> index a3e64e2..f26f515 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
>> @@ -1580,7 +1580,7 @@ static const struct amdgpu_ring_funcs
>> uvd_v6_0_enc_ring_vm_funcs = {
>> Â Â Â Â Â .set_wptr = uvd_v6_0_enc_ring_set_wptr,
>> Â Â Â Â Â .emit_frame_size =
>> Â Â Â Â Â Â Â Â Â 4 + /* uvd_v6_0_enc_ring_emit_pipeline_sync */
>> -Â Â Â Â Â Â Â 6 + /* uvd_v6_0_enc_ring_emit_vm_flush */
>> +Â Â Â Â Â Â Â 5 + /* uvd_v6_0_enc_ring_emit_vm_flush */
>> Â Â Â Â Â Â Â Â Â 5 + 5 + /* uvd_v6_0_enc_ring_emit_fence x2 vm fence */
>> Â Â Â Â Â Â Â Â Â 1, /* uvd_v6_0_enc_ring_insert_end */
>> Â Â Â Â Â .emit_ib_size = 5, /* uvd_v6_0_enc_ring_emit_ib */
>
