On Mon, Feb 26, 2018 at 12:18 AM, Monk Liu <Monk.Liu at amd.com> wrote:
> otherwise there will be DMAR reading error comes out from CP since
> GFX is still alive and CPC's WPTR_POLL is still enabled, which would
> lead to DMAR read error.
>
> fix:
> we can hault CPG after hw_fini, but cannot halt CPC becaues KIQ
> stil need to be alive to let RLCV invoke, but its WPTR_POLL could
> be disabled.
>
> Change-Id: Ia60ee54901531f737d09063bf2037630e7c94771
> Signed-off-by: Monk Liu <Monk.Liu at amd.com>
Is this handled properly for bare metal as well?
Alex
> ---
> drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> index e9cc03e..793db9f 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> @@ -2961,7 +2961,8 @@ static int gfx_v9_0_hw_fini(void *handle)
> gfx_v9_0_kcq_disable(&adev->gfx.kiq.ring, &adev->gfx.compute_ring[i]);
>
> if (amdgpu_sriov_vf(adev)) {
> - pr_debug("For SRIOV client, shouldn't do anything.\n");
> + gfx_v9_0_cp_gfx_enable(adev, false);
> + WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0);
> return 0;
> }
> gfx_v9_0_cp_enable(adev, false);
> --
> 2.7.4
>
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