[PATCH] drm/amd/pp: Add error handling when smu return failed on Vega10.

[Alexander.Deucher@xxxxxxx (Deucher, Alexander)]

Please include a commit message.  E.g.,


Clamp the clock index to a valid range when reading it back.


Or something like that.  With that fixed:

Reviewed-by: Alex Deucher <alexander.deucher at amd.com>

________________________________
From: amd-gfx <amd-gfx-bounces@xxxxxxxxxxxxxxxxxxxxx> on behalf of Rex Zhu <Rex.Zhu at amd.com>
Sent: Saturday, February 10, 2018 11:52:50 PM
To: amd-gfx at lists.freedesktop.org
Cc: Zhu, Rex
Subject: [PATCH] drm/amd/pp: Add error handling when smu return failed on Vega10.

Change-Id: I98032904fbb67db1d6b8a37842b340a5be339001
Signed-off-by: Rex Zhu <Rex.Zhu at amd.com>
---
 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 35 ++++++++++++----------
 1 file changed, 19 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
index 1a701c3..0430906 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
@@ -3945,28 +3945,31 @@ static int vega10_read_sensor(struct pp_hwmgr *hwmgr, int idx,

         switch (idx) {
         case AMDGPU_PP_SENSOR_GFX_SCLK:
-               ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentGfxclkIndex);
-               if (!ret) {
+                       smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentGfxclkIndex);
                         vega10_read_arg_from_smc(hwmgr, &sclk_idx);
-                       *((uint32_t *)value) = dpm_table->gfx_table.dpm_levels[sclk_idx].value;
-                       *size = 4;
+                       if (sclk_idx <  dpm_table->gfx_table.count) {
+                               *((uint32_t *)value) = dpm_table->gfx_table.dpm_levels[sclk_idx].value;
+                               *size = 4;
+                       } else {
+                               ret = -EINVAL;
+                       }
                 }
                 break;
         case AMDGPU_PP_SENSOR_GFX_MCLK:
-               ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentUclkIndex);
-               if (!ret) {
-                       vega10_read_arg_from_smc(hwmgr, &mclk_idx);
-                       *((uint32_t *)value) = dpm_table->mem_table.dpm_levels[mclk_idx].value;
-                       *size = 4;
-               }
+               smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentUclkIndex);
+               vega10_read_arg_from_smc(hwmgr, &mclk_idx);
+                       if (mclk_idx <  dpm_table->gfx_table.count) {
+                               *((uint32_t *)value) = dpm_table->mem_table.dpm_levels[mclk_idx].value;
+                               *size = 4;
+                       } else {
+                               ret = -EINVAL;
+                       }
                 break;
         case AMDGPU_PP_SENSOR_GPU_LOAD:
-               ret = smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetAverageGfxActivity, 0);
-               if (!ret) {
-                       vega10_read_arg_from_smc(hwmgr, &activity_percent);
-                       *((uint32_t *)value) = activity_percent > 100 ? 100 : activity_percent;
-                       *size = 4;
-               }
+               smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetAverageGfxActivity, 0);
+               vega10_read_arg_from_smc(hwmgr, &activity_percent);
+               *((uint32_t *)value) = activity_percent > 100 ? 100 : activity_percent;
+               *size = 4;
                 break;
         case AMDGPU_PP_SENSOR_GPU_TEMP:
                 *((uint32_t *)value) = vega10_thermal_get_temperature(hwmgr);
--
1.9.1

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