[PATCH 9/9] drm/amdgpu: program system bit for pte/pde when ZFB is enabled

[Feifei.Xu@xxxxxxx (Feifei Xu)]

Change-Id: Icfb8c1df201d3f22f1d8cdbaee55de6bebac8df6
Signed-off-by: Hawking Zhang <Hawking.Zhang at amd.com>
Acked-by: John Bridgman <john.bridgman at amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c | 2 ++
 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c    | 6 ++++++
 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c  | 2 ++
 3 files changed, 10 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
index f7e616b..dc1dc7c 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
@@ -47,6 +47,8 @@ static void gfxhub_v1_0_init_gart_pt_regs(struct amdgpu_device *adev)
 		+ adev->vm_manager.vram_base_offset;
 	value &= 0x0000FFFFFFFFF000ULL;
 	value |= 0x1; /*valid bit*/
+	if (adev->gmc.enable_zfb)
+		value |= 0x2; /*system bit*/
 
 	WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
 		     lower_32_bits(value));
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index 8fd7b01..48f71ac 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -470,6 +470,9 @@ static uint64_t gmc_v9_0_get_vm_pte_flags(struct amdgpu_device *adev,
 	if (flags & AMDGPU_VM_PAGE_WRITEABLE)
 		pte_flag |= AMDGPU_PTE_WRITEABLE;
 
+	if (adev->gmc.enable_zfb)
+		pte_flag |= AMDGPU_PTE_SYSTEM;
+
 	switch (flags & AMDGPU_VM_MTYPE_MASK) {
 	case AMDGPU_VM_MTYPE_DEFAULT:
 		pte_flag |= AMDGPU_PTE_MTYPE(MTYPE_NC);
@@ -505,6 +508,9 @@ static void gmc_v9_0_get_vm_pde(struct amdgpu_device *adev, int level,
 			adev->gmc.vram_start;
 	BUG_ON(*addr & 0xFFFF00000000003FULL);
 
+	if (adev->gmc.enable_zfb)
+		*flags |= AMDGPU_PTE_SYSTEM;
+
 	if (!adev->gmc.translate_further)
 		return;
 
diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
index c56ab47..5d94373 100644
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
@@ -57,6 +57,8 @@ static void mmhub_v1_0_init_gart_pt_regs(struct amdgpu_device *adev)
 		adev->vm_manager.vram_base_offset;
 	value &= 0x0000FFFFFFFFF000ULL;
 	value |= 0x1; /* valid bit */
+	if (adev->gmc.enable_zfb)
+		value |= 0x2; /* system bit*/
 
 	WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
 		     lower_32_bits(value));
-- 
2.7.4