Could we cache the previous VMID/PASID mapping somewhere, and only update+wait if it changes? If this is not the right place to check it (because multiple rings can be using the same VMID concurrently), maybe add a flag to emit_flush_gpu_tlb to update the PASID mapping conditionally, and make the decision higher up in then VM manager. Regards,  Felix On 2018-01-26 03:13 PM, Christian König wrote: > Update the PASID in the ATC as well and wait for the update to finish. > > Signed-off-by: Christian König <christian.koenig at amd.com> > --- > drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 21 ++++++++++++++++++++- > drivers/gpu/drm/amd/amdgpu/soc15.h | 4 ++-- > 2 files changed, 22 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c > index 2c60981d2eec..0077db0a451f 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c > @@ -33,6 +33,7 @@ > #include "vega10_enum.h" > #include "mmhub/mmhub_1_0_offset.h" > #include "athub/athub_1_0_offset.h" > +#include "athub/athub_1_0_sh_mask.h" > #include "oss/osssys_4_0_offset.h" > > #include "soc15.h" > @@ -375,7 +376,7 @@ static uint64_t gmc_v9_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring, > uint32_t req = gmc_v9_0_get_invalidate_req(vmid); > uint64_t flags = AMDGPU_PTE_VALID; > unsigned eng = ring->vm_inv_eng; > - uint32_t reg; > + uint32_t reg, val; > > amdgpu_gmc_get_vm_pde(ring->adev, -1, &pd_addr, &flags); > pd_addr |= flags; > @@ -393,8 +394,26 @@ static uint64_t gmc_v9_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring, > > amdgpu_ring_emit_wreg(ring, reg, pasid); > > + if (ring->funcs->vmhub == AMDGPU_GFXHUB) > + reg = SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING) + vmid; > + else > + reg = SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID16_PASID_MAPPING) + vmid; > + > + val = 0; > + val = REG_SET_FIELD(val, ATC_VMID0_PASID_MAPPING, PASID, pasid); > + val = REG_SET_FIELD(val, ATC_VMID0_PASID_MAPPING, VALID, 1); > + amdgpu_ring_emit_wreg(ring, reg, val); > + > amdgpu_ring_emit_wreg(ring, hub->vm_inv_eng0_req + eng, req); > > + /* wait for the ATC to complete */ > + reg = SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID_PASID_MAPPING_UPDATE_STATUS); > + if (ring->funcs->vmhub == AMDGPU_GFXHUB) > + val = 0x1 << vmid; > + else > + val = 0x10000 << vmid; > + amdgpu_ring_emit_reg_wait(ring, reg, val, val); > + > /* wait for the invalidate to complete */ > amdgpu_ring_emit_reg_wait(ring, hub->vm_inv_eng0_ack + eng, > 1 << vmid, 1 << vmid); > diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.h b/drivers/gpu/drm/amd/amdgpu/soc15.h > index f70da8a29f86..1b8833503f4c 100644 > --- a/drivers/gpu/drm/amd/amdgpu/soc15.h > +++ b/drivers/gpu/drm/amd/amdgpu/soc15.h > @@ -27,8 +27,8 @@ > #include "nbio_v6_1.h" > #include "nbio_v7_0.h" > > -#define SOC15_FLUSH_GPU_TLB_NUM_WREG 4 > -#define SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT 1 > +#define SOC15_FLUSH_GPU_TLB_NUM_WREG 5 > +#define SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT 2 > > extern const struct amd_ip_funcs soc15_common_ip_funcs; >
