[PATCH 1/2] drm/amdgpu/psp: use a function pointer structure

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Am 23.01.2018 um 22:29 schrieb Alex Deucher:
> This way we can make all of the IP specific functions static,
> and we only need a single entry point into the PSP IP modules.
>
> Signed-off-by: Alex Deucher <alexander.deucher at amd.com>

Reviewed-by: Christian König <christian.koenig at amd.com> for the series.

> ---
>   drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 23 +-----------
>   drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | 41 ++++++++++++---------
>   drivers/gpu/drm/amd/amdgpu/psp_v10_0.c  | 56 +++++++++++++++++++---------
>   drivers/gpu/drm/amd/amdgpu/psp_v10_0.h  | 20 +---------
>   drivers/gpu/drm/amd/amdgpu/psp_v3_1.c   | 65 +++++++++++++++++++++++----------
>   drivers/gpu/drm/amd/amdgpu/psp_v3_1.h   | 24 +-----------
>   6 files changed, 113 insertions(+), 116 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
> index 2157d4509e84..e6cb9e2896f1 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
> @@ -51,29 +51,10 @@ static int psp_sw_init(void *handle)
>   
>   	switch (adev->asic_type) {
>   	case CHIP_VEGA10:
> -		psp->init_microcode = psp_v3_1_init_microcode;
> -		psp->bootloader_load_sysdrv = psp_v3_1_bootloader_load_sysdrv;
> -		psp->bootloader_load_sos = psp_v3_1_bootloader_load_sos;
> -		psp->prep_cmd_buf = psp_v3_1_prep_cmd_buf;
> -		psp->ring_init = psp_v3_1_ring_init;
> -		psp->ring_create = psp_v3_1_ring_create;
> -		psp->ring_stop = psp_v3_1_ring_stop;
> -		psp->ring_destroy = psp_v3_1_ring_destroy;
> -		psp->cmd_submit = psp_v3_1_cmd_submit;
> -		psp->compare_sram_data = psp_v3_1_compare_sram_data;
> -		psp->smu_reload_quirk = psp_v3_1_smu_reload_quirk;
> -		psp->mode1_reset = psp_v3_1_mode1_reset;
> +		psp_v3_1_set_psp_funcs(psp);
>   		break;
>   	case CHIP_RAVEN:
> -		psp->init_microcode = psp_v10_0_init_microcode;
> -		psp->prep_cmd_buf = psp_v10_0_prep_cmd_buf;
> -		psp->ring_init = psp_v10_0_ring_init;
> -		psp->ring_create = psp_v10_0_ring_create;
> -		psp->ring_stop = psp_v10_0_ring_stop;
> -		psp->ring_destroy = psp_v10_0_ring_destroy;
> -		psp->cmd_submit = psp_v10_0_cmd_submit;
> -		psp->compare_sram_data = psp_v10_0_compare_sram_data;
> -		psp->mode1_reset = psp_v10_0_mode1_reset;
> +		psp_v10_0_set_psp_funcs(psp);
>   		break;
>   	default:
>   		return -EINVAL;
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
> index ce4654550416..cf28abc5ccbf 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
> @@ -33,6 +33,8 @@
>   #define PSP_ASD_SHARED_MEM_SIZE	0x4000
>   #define PSP_1_MEG		0x100000
>   
> +struct psp_context;
> +
>   enum psp_ring_type
>   {
>   	PSP_RING_TYPE__INVALID = 0,
> @@ -53,12 +55,8 @@ struct psp_ring
>   	uint32_t			ring_size;
>   };
>   
> -struct psp_context
> +struct psp_funcs
>   {
> -	struct amdgpu_device            *adev;
> -	struct psp_ring                 km_ring;
> -	struct psp_gfx_cmd_resp		*cmd;
> -
>   	int (*init_microcode)(struct psp_context *psp);
>   	int (*bootloader_load_sysdrv)(struct psp_context *psp);
>   	int (*bootloader_load_sos)(struct psp_context *psp);
> @@ -77,6 +75,15 @@ struct psp_context
>   				  enum AMDGPU_UCODE_ID ucode_type);
>   	bool (*smu_reload_quirk)(struct psp_context *psp);
>   	int (*mode1_reset)(struct psp_context *psp);
> +};
> +
> +struct psp_context
> +{
> +	struct amdgpu_device            *adev;
> +	struct psp_ring                 km_ring;
> +	struct psp_gfx_cmd_resp		*cmd;
> +
> +	const struct psp_funcs 		*funcs;
>   
>   	/* fence buffer */
>   	struct amdgpu_bo 		*fw_pri_bo;
> @@ -123,25 +130,25 @@ struct amdgpu_psp_funcs {
>   					enum AMDGPU_UCODE_ID);
>   };
>   
> -#define psp_prep_cmd_buf(ucode, type) (psp)->prep_cmd_buf((ucode), (type))
> -#define psp_ring_init(psp, type) (psp)->ring_init((psp), (type))
> -#define psp_ring_create(psp, type) (psp)->ring_create((psp), (type))
> -#define psp_ring_stop(psp, type) (psp)->ring_stop((psp), (type))
> -#define psp_ring_destroy(psp, type) ((psp)->ring_destroy((psp), (type)))
> +#define psp_prep_cmd_buf(ucode, type) (psp)->funcs->prep_cmd_buf((ucode), (type))
> +#define psp_ring_init(psp, type) (psp)->funcs->ring_init((psp), (type))
> +#define psp_ring_create(psp, type) (psp)->funcs->ring_create((psp), (type))
> +#define psp_ring_stop(psp, type) (psp)->funcs->ring_stop((psp), (type))
> +#define psp_ring_destroy(psp, type) ((psp)->funcs->ring_destroy((psp), (type)))
>   #define psp_cmd_submit(psp, ucode, cmd_mc, fence_mc, index) \
> -		(psp)->cmd_submit((psp), (ucode), (cmd_mc), (fence_mc), (index))
> +		(psp)->funcs->cmd_submit((psp), (ucode), (cmd_mc), (fence_mc), (index))
>   #define psp_compare_sram_data(psp, ucode, type) \
> -		(psp)->compare_sram_data((psp), (ucode), (type))
> +		(psp)->funcs->compare_sram_data((psp), (ucode), (type))
>   #define psp_init_microcode(psp) \
> -		((psp)->init_microcode ? (psp)->init_microcode((psp)) : 0)
> +		((psp)->funcs->init_microcode ? (psp)->funcs->init_microcode((psp)) : 0)
>   #define psp_bootloader_load_sysdrv(psp) \
> -		((psp)->bootloader_load_sysdrv ? (psp)->bootloader_load_sysdrv((psp)) : 0)
> +		((psp)->funcs->bootloader_load_sysdrv ? (psp)->funcs->bootloader_load_sysdrv((psp)) : 0)
>   #define psp_bootloader_load_sos(psp) \
> -		((psp)->bootloader_load_sos ? (psp)->bootloader_load_sos((psp)) : 0)
> +		((psp)->funcs->bootloader_load_sos ? (psp)->funcs->bootloader_load_sos((psp)) : 0)
>   #define psp_smu_reload_quirk(psp) \
> -		((psp)->smu_reload_quirk ? (psp)->smu_reload_quirk((psp)) : false)
> +		((psp)->funcs->smu_reload_quirk ? (psp)->funcs->smu_reload_quirk((psp)) : false)
>   #define psp_mode1_reset(psp) \
> -		((psp)->mode1_reset ? (psp)->mode1_reset((psp)) : false)
> +		((psp)->funcs->mode1_reset ? (psp)->funcs->mode1_reset((psp)) : false)
>   
>   extern const struct amd_ip_funcs psp_ip_funcs;
>   
> diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
> index 5a9fe24697f9..8873d833a7f7 100644
> --- a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
> @@ -87,7 +87,7 @@ psp_v10_0_get_fw_type(struct amdgpu_firmware_info *ucode, enum psp_gfx_fw_type *
>   	return 0;
>   }
>   
> -int psp_v10_0_init_microcode(struct psp_context *psp)
> +static int psp_v10_0_init_microcode(struct psp_context *psp)
>   {
>   	struct amdgpu_device *adev = psp->adev;
>   	const char *chip_name;
> @@ -133,7 +133,8 @@ int psp_v10_0_init_microcode(struct psp_context *psp)
>   	return err;
>   }
>   
> -int psp_v10_0_prep_cmd_buf(struct amdgpu_firmware_info *ucode, struct psp_gfx_cmd_resp *cmd)
> +static int psp_v10_0_prep_cmd_buf(struct amdgpu_firmware_info *ucode,
> +				  struct psp_gfx_cmd_resp *cmd)
>   {
>   	int ret;
>   	uint64_t fw_mem_mc_addr = ucode->mc_addr;
> @@ -152,7 +153,8 @@ int psp_v10_0_prep_cmd_buf(struct amdgpu_firmware_info *ucode, struct psp_gfx_cm
>   	return ret;
>   }
>   
> -int psp_v10_0_ring_init(struct psp_context *psp, enum psp_ring_type ring_type)
> +static int psp_v10_0_ring_init(struct psp_context *psp,
> +			       enum psp_ring_type ring_type)
>   {
>   	int ret = 0;
>   	struct psp_ring *ring;
> @@ -177,7 +179,8 @@ int psp_v10_0_ring_init(struct psp_context *psp, enum psp_ring_type ring_type)
>   	return 0;
>   }
>   
> -int psp_v10_0_ring_create(struct psp_context *psp, enum psp_ring_type ring_type)
> +static int psp_v10_0_ring_create(struct psp_context *psp,
> +				 enum psp_ring_type ring_type)
>   {
>   	int ret = 0;
>   	unsigned int psp_ring_reg = 0;
> @@ -208,7 +211,8 @@ int psp_v10_0_ring_create(struct psp_context *psp, enum psp_ring_type ring_type)
>   	return ret;
>   }
>   
> -int psp_v10_0_ring_stop(struct psp_context *psp, enum psp_ring_type ring_type)
> +static int psp_v10_0_ring_stop(struct psp_context *psp,
> +			       enum psp_ring_type ring_type)
>   {
>   	int ret = 0;
>   	struct psp_ring *ring;
> @@ -231,7 +235,8 @@ int psp_v10_0_ring_stop(struct psp_context *psp, enum psp_ring_type ring_type)
>   	return ret;
>   }
>   
> -int psp_v10_0_ring_destroy(struct psp_context *psp, enum psp_ring_type ring_type)
> +static int psp_v10_0_ring_destroy(struct psp_context *psp,
> +				  enum psp_ring_type ring_type)
>   {
>   	int ret = 0;
>   	struct psp_ring *ring = &psp->km_ring;
> @@ -248,10 +253,10 @@ int psp_v10_0_ring_destroy(struct psp_context *psp, enum psp_ring_type ring_type
>   	return ret;
>   }
>   
> -int psp_v10_0_cmd_submit(struct psp_context *psp,
> -		        struct amdgpu_firmware_info *ucode,
> -		        uint64_t cmd_buf_mc_addr, uint64_t fence_mc_addr,
> -		        int index)
> +static int psp_v10_0_cmd_submit(struct psp_context *psp,
> +				struct amdgpu_firmware_info *ucode,
> +				uint64_t cmd_buf_mc_addr, uint64_t fence_mc_addr,
> +				int index)
>   {
>   	unsigned int psp_write_ptr_reg = 0;
>   	struct psp_gfx_rb_frame * write_frame = psp->km_ring.ring_mem;
> @@ -298,9 +303,9 @@ int psp_v10_0_cmd_submit(struct psp_context *psp,
>   
>   static int
>   psp_v10_0_sram_map(struct amdgpu_device *adev,
> -		unsigned int *sram_offset, unsigned int *sram_addr_reg_offset,
> -		unsigned int *sram_data_reg_offset,
> -		enum AMDGPU_UCODE_ID ucode_id)
> +		   unsigned int *sram_offset, unsigned int *sram_addr_reg_offset,
> +		   unsigned int *sram_data_reg_offset,
> +		   enum AMDGPU_UCODE_ID ucode_id)
>   {
>   	int ret = 0;
>   
> @@ -383,9 +388,9 @@ psp_v10_0_sram_map(struct amdgpu_device *adev,
>   	return ret;
>   }
>   
> -bool psp_v10_0_compare_sram_data(struct psp_context *psp,
> -				struct amdgpu_firmware_info *ucode,
> -				enum AMDGPU_UCODE_ID ucode_type)
> +static bool psp_v10_0_compare_sram_data(struct psp_context *psp,
> +					struct amdgpu_firmware_info *ucode,
> +					enum AMDGPU_UCODE_ID ucode_type)
>   {
>   	int err = 0;
>   	unsigned int fw_sram_reg_val = 0;
> @@ -419,8 +424,25 @@ bool psp_v10_0_compare_sram_data(struct psp_context *psp,
>   }
>   
>   
> -int psp_v10_0_mode1_reset(struct psp_context *psp)
> +static int psp_v10_0_mode1_reset(struct psp_context *psp)
>   {
>   	DRM_INFO("psp mode 1 reset not supported now! \n");
>   	return -EINVAL;
>   }
> +
> +static const struct psp_funcs psp_v10_0_funcs = {
> +	.init_microcode = psp_v10_0_init_microcode,
> +	.prep_cmd_buf = psp_v10_0_prep_cmd_buf,
> +	.ring_init = psp_v10_0_ring_init,
> +	.ring_create = psp_v10_0_ring_create,
> +	.ring_stop = psp_v10_0_ring_stop,
> +	.ring_destroy = psp_v10_0_ring_destroy,
> +	.cmd_submit = psp_v10_0_cmd_submit,
> +	.compare_sram_data = psp_v10_0_compare_sram_data,
> +	.mode1_reset = psp_v10_0_mode1_reset,
> +};
> +
> +void psp_v10_0_set_psp_funcs(struct psp_context *psp)
> +{
> +	psp->funcs = &psp_v10_0_funcs;
> +}
> diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.h b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.h
> index 451e8308303f..20c2a94859d8 100644
> --- a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.h
> +++ b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.h
> @@ -27,24 +27,6 @@
>   
>   #include "amdgpu_psp.h"
>   
> -extern int psp_v10_0_init_microcode(struct psp_context *psp);
> -extern int psp_v10_0_prep_cmd_buf(struct amdgpu_firmware_info *ucode,
> -				 struct psp_gfx_cmd_resp *cmd);
> -extern int psp_v10_0_ring_init(struct psp_context *psp,
> -			      enum psp_ring_type ring_type);
> -extern int psp_v10_0_ring_create(struct psp_context *psp,
> -				 enum psp_ring_type ring_type);
> -extern int psp_v10_0_ring_stop(struct psp_context *psp,
> -				  enum psp_ring_type ring_type);
> -extern int psp_v10_0_ring_destroy(struct psp_context *psp,
> -				  enum psp_ring_type ring_type);
> -extern int psp_v10_0_cmd_submit(struct psp_context *psp,
> -			       struct amdgpu_firmware_info *ucode,
> -			       uint64_t cmd_buf_mc_addr, uint64_t fence_mc_addr,
> -			       int index);
> -extern bool psp_v10_0_compare_sram_data(struct psp_context *psp,
> -				       struct amdgpu_firmware_info *ucode,
> -				       enum AMDGPU_UCODE_ID ucode_type);
> +void psp_v10_0_set_psp_funcs(struct psp_context *psp);
>   
> -extern int psp_v10_0_mode1_reset(struct psp_context *psp);
>   #endif
> diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
> index 19bd1934e63d..690b9766d8ae 100644
> --- a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
> +++ b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.c
> @@ -93,7 +93,7 @@ psp_v3_1_get_fw_type(struct amdgpu_firmware_info *ucode, enum psp_gfx_fw_type *t
>   	return 0;
>   }
>   
> -int psp_v3_1_init_microcode(struct psp_context *psp)
> +static int psp_v3_1_init_microcode(struct psp_context *psp)
>   {
>   	struct amdgpu_device *adev = psp->adev;
>   	const char *chip_name;
> @@ -161,7 +161,7 @@ int psp_v3_1_init_microcode(struct psp_context *psp)
>   	return err;
>   }
>   
> -int psp_v3_1_bootloader_load_sysdrv(struct psp_context *psp)
> +static int psp_v3_1_bootloader_load_sysdrv(struct psp_context *psp)
>   {
>   	int ret;
>   	uint32_t psp_gfxdrv_command_reg = 0;
> @@ -202,7 +202,7 @@ int psp_v3_1_bootloader_load_sysdrv(struct psp_context *psp)
>   	return ret;
>   }
>   
> -int psp_v3_1_bootloader_load_sos(struct psp_context *psp)
> +static int psp_v3_1_bootloader_load_sos(struct psp_context *psp)
>   {
>   	int ret;
>   	unsigned int psp_gfxdrv_command_reg = 0;
> @@ -243,7 +243,8 @@ int psp_v3_1_bootloader_load_sos(struct psp_context *psp)
>   	return ret;
>   }
>   
> -int psp_v3_1_prep_cmd_buf(struct amdgpu_firmware_info *ucode, struct psp_gfx_cmd_resp *cmd)
> +static int psp_v3_1_prep_cmd_buf(struct amdgpu_firmware_info *ucode,
> +				 struct psp_gfx_cmd_resp *cmd)
>   {
>   	int ret;
>   	uint64_t fw_mem_mc_addr = ucode->mc_addr;
> @@ -262,7 +263,8 @@ int psp_v3_1_prep_cmd_buf(struct amdgpu_firmware_info *ucode, struct psp_gfx_cmd
>   	return ret;
>   }
>   
> -int psp_v3_1_ring_init(struct psp_context *psp, enum psp_ring_type ring_type)
> +static int psp_v3_1_ring_init(struct psp_context *psp,
> +			      enum psp_ring_type ring_type)
>   {
>   	int ret = 0;
>   	struct psp_ring *ring;
> @@ -287,7 +289,8 @@ int psp_v3_1_ring_init(struct psp_context *psp, enum psp_ring_type ring_type)
>   	return 0;
>   }
>   
> -int psp_v3_1_ring_create(struct psp_context *psp, enum psp_ring_type ring_type)
> +static int psp_v3_1_ring_create(struct psp_context *psp,
> +				enum psp_ring_type ring_type)
>   {
>   	int ret = 0;
>   	unsigned int psp_ring_reg = 0;
> @@ -318,7 +321,8 @@ int psp_v3_1_ring_create(struct psp_context *psp, enum psp_ring_type ring_type)
>   	return ret;
>   }
>   
> -int psp_v3_1_ring_stop(struct psp_context *psp, enum psp_ring_type ring_type)
> +static int psp_v3_1_ring_stop(struct psp_context *psp,
> +			      enum psp_ring_type ring_type)
>   {
>   	int ret = 0;
>   	struct psp_ring *ring;
> @@ -341,7 +345,8 @@ int psp_v3_1_ring_stop(struct psp_context *psp, enum psp_ring_type ring_type)
>   	return ret;
>   }
>   
> -int psp_v3_1_ring_destroy(struct psp_context *psp, enum psp_ring_type ring_type)
> +static int psp_v3_1_ring_destroy(struct psp_context *psp,
> +				 enum psp_ring_type ring_type)
>   {
>   	int ret = 0;
>   	struct psp_ring *ring = &psp->km_ring;
> @@ -358,10 +363,10 @@ int psp_v3_1_ring_destroy(struct psp_context *psp, enum psp_ring_type ring_type)
>   	return ret;
>   }
>   
> -int psp_v3_1_cmd_submit(struct psp_context *psp,
> -		        struct amdgpu_firmware_info *ucode,
> -		        uint64_t cmd_buf_mc_addr, uint64_t fence_mc_addr,
> -		        int index)
> +static int psp_v3_1_cmd_submit(struct psp_context *psp,
> +			       struct amdgpu_firmware_info *ucode,
> +			       uint64_t cmd_buf_mc_addr, uint64_t fence_mc_addr,
> +			       int index)
>   {
>   	unsigned int psp_write_ptr_reg = 0;
>   	struct psp_gfx_rb_frame * write_frame = psp->km_ring.ring_mem;
> @@ -410,9 +415,9 @@ int psp_v3_1_cmd_submit(struct psp_context *psp,
>   
>   static int
>   psp_v3_1_sram_map(struct amdgpu_device *adev,
> -		unsigned int *sram_offset, unsigned int *sram_addr_reg_offset,
> -		unsigned int *sram_data_reg_offset,
> -		enum AMDGPU_UCODE_ID ucode_id)
> +		  unsigned int *sram_offset, unsigned int *sram_addr_reg_offset,
> +		  unsigned int *sram_data_reg_offset,
> +		  enum AMDGPU_UCODE_ID ucode_id)
>   {
>   	int ret = 0;
>   
> @@ -495,9 +500,9 @@ psp_v3_1_sram_map(struct amdgpu_device *adev,
>   	return ret;
>   }
>   
> -bool psp_v3_1_compare_sram_data(struct psp_context *psp,
> -				struct amdgpu_firmware_info *ucode,
> -				enum AMDGPU_UCODE_ID ucode_type)
> +static bool psp_v3_1_compare_sram_data(struct psp_context *psp,
> +				       struct amdgpu_firmware_info *ucode,
> +				       enum AMDGPU_UCODE_ID ucode_type)
>   {
>   	int err = 0;
>   	unsigned int fw_sram_reg_val = 0;
> @@ -530,7 +535,7 @@ bool psp_v3_1_compare_sram_data(struct psp_context *psp,
>   	return true;
>   }
>   
> -bool psp_v3_1_smu_reload_quirk(struct psp_context *psp)
> +static bool psp_v3_1_smu_reload_quirk(struct psp_context *psp)
>   {
>   	struct amdgpu_device *adev = psp->adev;
>   	uint32_t reg;
> @@ -541,7 +546,7 @@ bool psp_v3_1_smu_reload_quirk(struct psp_context *psp)
>   	return (reg & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) ? true : false;
>   }
>   
> -int psp_v3_1_mode1_reset(struct psp_context *psp)
> +static int psp_v3_1_mode1_reset(struct psp_context *psp)
>   {
>   	int ret;
>   	uint32_t offset;
> @@ -574,3 +579,23 @@ int psp_v3_1_mode1_reset(struct psp_context *psp)
>   
>   	return 0;
>   }
> +
> +static const struct psp_funcs psp_v3_1_funcs = {
> +	.init_microcode = psp_v3_1_init_microcode,
> +	.bootloader_load_sysdrv = psp_v3_1_bootloader_load_sysdrv,
> +	.bootloader_load_sos = psp_v3_1_bootloader_load_sos,
> +	.prep_cmd_buf = psp_v3_1_prep_cmd_buf,
> +	.ring_init = psp_v3_1_ring_init,
> +	.ring_create = psp_v3_1_ring_create,
> +	.ring_stop = psp_v3_1_ring_stop,
> +	.ring_destroy = psp_v3_1_ring_destroy,
> +	.cmd_submit = psp_v3_1_cmd_submit,
> +	.compare_sram_data = psp_v3_1_compare_sram_data,
> +	.smu_reload_quirk = psp_v3_1_smu_reload_quirk,
> +	.mode1_reset = psp_v3_1_mode1_reset,
> +};
> +
> +void psp_v3_1_set_psp_funcs(struct psp_context *psp)
> +{
> +	psp->funcs = &psp_v3_1_funcs;
> +}
> diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.h b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.h
> index b05dbada7751..e411e31ba452 100644
> --- a/drivers/gpu/drm/amd/amdgpu/psp_v3_1.h
> +++ b/drivers/gpu/drm/amd/amdgpu/psp_v3_1.h
> @@ -32,26 +32,6 @@ enum { PSP_BINARY_ALIGNMENT = 64 };
>   enum { PSP_BOOTLOADER_1_MEG_ALIGNMENT = 0x100000 };
>   enum { PSP_BOOTLOADER_8_MEM_ALIGNMENT = 0x800000 };
>   
> -extern int psp_v3_1_init_microcode(struct psp_context *psp);
> -extern int psp_v3_1_bootloader_load_sysdrv(struct psp_context *psp);
> -extern int psp_v3_1_bootloader_load_sos(struct psp_context *psp);
> -extern int psp_v3_1_prep_cmd_buf(struct amdgpu_firmware_info *ucode,
> -				 struct psp_gfx_cmd_resp *cmd);
> -extern int psp_v3_1_ring_init(struct psp_context *psp,
> -			      enum psp_ring_type ring_type);
> -extern int psp_v3_1_ring_create(struct psp_context *psp,
> -				enum psp_ring_type ring_type);
> -extern int psp_v3_1_ring_stop(struct psp_context *psp,
> -				enum psp_ring_type ring_type);
> -extern int psp_v3_1_ring_destroy(struct psp_context *psp,
> -				enum psp_ring_type ring_type);
> -extern int psp_v3_1_cmd_submit(struct psp_context *psp,
> -			       struct amdgpu_firmware_info *ucode,
> -			       uint64_t cmd_buf_mc_addr, uint64_t fence_mc_addr,
> -			       int index);
> -extern bool psp_v3_1_compare_sram_data(struct psp_context *psp,
> -				       struct amdgpu_firmware_info *ucode,
> -				       enum AMDGPU_UCODE_ID ucode_type);
> -extern bool psp_v3_1_smu_reload_quirk(struct psp_context *psp);
> -extern int psp_v3_1_mode1_reset(struct psp_context *psp);
> +void psp_v3_1_set_psp_funcs(struct psp_context *psp);
> +
>   #endif



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