On 2018-01-22 08:45 AM, Huang Rui wrote: > It must use queue id 0, because CGPG_IDLE/SAVE/LOAD/RUN only can be issued on > queue 0. > > Signed-off-by: Huang Rui <ray.huang at amd.com> > Acked-by: Hawking Zhang <Hawking.Zhang at amd.com> > Reviewed-by: Alex Deucher <alexander.deucher at amd.com> > --- > drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 8 ++++++-- > 1 file changed, 6 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c > index ef04336..0cfb939 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c > @@ -179,8 +179,12 @@ static int amdgpu_gfx_kiq_acquire(struct amdgpu_device *adev, > > amdgpu_gfx_bit_to_queue(adev, queue_bit, &mec, &pipe, &queue); > > - /* Using pipes 2/3 from MEC 2 seems cause problems */ > - if (mec == 1 && pipe > 1) > + /* > + * 1. Using pipes 2/3 from MEC 2 seems cause problems.' Could this have been related to #2? Should we just simplify this by guaranteeing KIQ MEC[0] PIPE[0] QUEUE[0]? Regards, Andres > + * 2. It must use queue id 0, because CGPG_IDLE/SAVE/LOAD/RUN > + * only can be issued on queue 0. > + */ > + if ((mec == 1 && pipe > 1) || queue != 0) > continue; > > ring->me = mec + 1; >
