On 01/11/2018 10:50 AM, Chunming Zhou wrote: > Could I how to verify this is valid fix? For now, check if there is no vm fault or any other side effect when loading amdgpu with ngg=1. Later development will be implemented with OGL team together. Jerry > > Regards, > > David Zhou > > > On 2018å¹´01æ??11æ?¥ 10:30, Junwei Zhang wrote: >> v2: fix register access >> >> Signed-off-by: Junwei Zhang <Jerry.Zhang at amd.com> >> --- >> drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 9 +++++---- >> 1 file changed, 5 insertions(+), 4 deletions(-) >> >> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c >> b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c >> index ae976e3..6db3645 100644 >> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c >> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c >> @@ -1068,8 +1068,8 @@ static int gfx_v9_0_ngg_init(struct amdgpu_device *adev) >> adev->gfx.ngg.gds_reserve_size = ALIGN(5 * 4, 0x40); >> adev->gds.mem.total_size -= adev->gfx.ngg.gds_reserve_size; >> adev->gds.mem.gfx_partition_size -= adev->gfx.ngg.gds_reserve_size; >> - adev->gfx.ngg.gds_reserve_addr = SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE); >> - adev->gfx.ngg.gds_reserve_addr += adev->gds.mem.gfx_partition_size; >> + adev->gfx.ngg.gds_reserve_addr = RREG32_SOC15(GC, 0, mmGDS_VMID0_BASE); >> + adev->gfx.ngg.gds_reserve_addr += RREG32_SOC15(GC, 0, mmGDS_VMID0_SIZE); >> /* Primitive Buffer */ >> r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_PRIM], >> @@ -1181,13 +1181,14 @@ static int gfx_v9_0_ngg_en(struct amdgpu_device *adev) >> amdgpu_ring_write(ring, PACKET3(PACKET3_DMA_DATA, 5)); >> amdgpu_ring_write(ring, (PACKET3_DMA_DATA_CP_SYNC | >> + PACKET3_DMA_DATA_DST_SEL(1) | >> PACKET3_DMA_DATA_SRC_SEL(2))); >> amdgpu_ring_write(ring, 0); >> amdgpu_ring_write(ring, 0); >> amdgpu_ring_write(ring, adev->gfx.ngg.gds_reserve_addr); >> amdgpu_ring_write(ring, 0); >> - amdgpu_ring_write(ring, adev->gfx.ngg.gds_reserve_size); >> - >> + amdgpu_ring_write(ring, PACKET3_DMA_DATA_CMD_RAW_WAIT | >> + adev->gfx.ngg.gds_reserve_size); >> gfx_v9_0_write_data_to_reg(ring, 0, false, >> SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE), 0); >
