[PATCH] drm/amd/pp: Refine code shorten variable name

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Reviewed-by: Alex Deucher <alexander.deucher at amd.com>

________________________________
From: amd-gfx <amd-gfx-bounces@xxxxxxxxxxxxxxxxxxxxx> on behalf of Rex Zhu <Rex.Zhu at amd.com>
Sent: Thursday, January 4, 2018 4:56:56 AM
To: amd-gfx at lists.freedesktop.org
Cc: Zhu, Rex
Subject: [PATCH] drm/amd/pp: Refine code shorten variable name

Change-Id: Id5f146321b11c9dbfa5a48a5197e714761f57670
Signed-off-by: Rex Zhu <Rex.Zhu at amd.com>
---
 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 24 ++++++++--------------
 .../gpu/drm/amd/powerplay/inc/hardwaremanager.h    |  2 +-
 2 files changed, 9 insertions(+), 17 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
index 3d729f0..4219004 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
@@ -1387,11 +1387,9 @@ static int vega10_setup_default_dpm_tables(struct pp_hwmgr *hwmgr)
                 data->odn_dpm_table.odn_core_clock_dpm_levels.
                 number_of_performance_levels = data->dpm_table.gfx_table.count;
                 for (i = 0; i < data->dpm_table.gfx_table.count; i++) {
-                       data->odn_dpm_table.odn_core_clock_dpm_levels.
-                       performance_level_entries[i].clock =
+                       data->odn_dpm_table.odn_core_clock_dpm_levels.entries[i].clock =
                                         data->dpm_table.gfx_table.dpm_levels[i].value;
-                       data->odn_dpm_table.odn_core_clock_dpm_levels.
-                       performance_level_entries[i].enabled = true;
+                       data->odn_dpm_table.odn_core_clock_dpm_levels.entries[i].enabled = true;
                 }

                 data->odn_dpm_table.vdd_dependency_on_sclk.count =
@@ -1410,11 +1408,9 @@ static int vega10_setup_default_dpm_tables(struct pp_hwmgr *hwmgr)
                 data->odn_dpm_table.odn_memory_clock_dpm_levels.
                 number_of_performance_levels = data->dpm_table.mem_table.count;
                 for (i = 0; i < data->dpm_table.mem_table.count; i++) {
-                       data->odn_dpm_table.odn_memory_clock_dpm_levels.
-                       performance_level_entries[i].clock =
+                       data->odn_dpm_table.odn_memory_clock_dpm_levels.entries[i].clock =
                                         data->dpm_table.mem_table.dpm_levels[i].value;
-                       data->odn_dpm_table.odn_memory_clock_dpm_levels.
-                       performance_level_entries[i].enabled = true;
+                       data->odn_dpm_table.odn_memory_clock_dpm_levels.entries[i].enabled = true;
                 }

                 data->odn_dpm_table.vdd_dependency_on_mclk.count = dep_mclk_table->count;
@@ -3352,11 +3348,9 @@ static int vega10_populate_and_upload_sclk_mclk_dpm_levels(
                                         dpm_count < dpm_table->gfx_table.count;
                                         dpm_count++) {
                                 dpm_table->gfx_table.dpm_levels[dpm_count].enabled =
-                                               data->odn_dpm_table.odn_core_clock_dpm_levels.
-                                               performance_level_entries[dpm_count].enabled;
+                                       data->odn_dpm_table.odn_core_clock_dpm_levels.entries[dpm_count].enabled;
                                 dpm_table->gfx_table.dpm_levels[dpm_count].value =
-                                               data->odn_dpm_table.odn_core_clock_dpm_levels.
-                                               performance_level_entries[dpm_count].clock;
+                                       data->odn_dpm_table.odn_core_clock_dpm_levels.entries[dpm_count].clock;
                         }
                 }

@@ -3366,11 +3360,9 @@ static int vega10_populate_and_upload_sclk_mclk_dpm_levels(
                                         dpm_count < dpm_table->mem_table.count;
                                         dpm_count++) {
                                 dpm_table->mem_table.dpm_levels[dpm_count].enabled =
-                                               data->odn_dpm_table.odn_memory_clock_dpm_levels.
-                                               performance_level_entries[dpm_count].enabled;
+                                       data->odn_dpm_table.odn_memory_clock_dpm_levels.entries[dpm_count].enabled;
                                 dpm_table->mem_table.dpm_levels[dpm_count].value =
-                                               data->odn_dpm_table.odn_memory_clock_dpm_levels.
-                                               performance_level_entries[dpm_count].clock;
+                                       data->odn_dpm_table.odn_memory_clock_dpm_levels.entries[dpm_count].clock;
                         }
                 }

diff --git a/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h b/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h
index f919301..933aa44 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h
@@ -370,7 +370,7 @@ struct phm_odn_clock_levels {
         uint32_t flags;
         uint32_t number_of_performance_levels;
         /* variable-sized array, specify by ulNumberOfPerformanceLevels. */
-       struct phm_odn_performance_level performance_level_entries[8];
+       struct phm_odn_performance_level entries[8];
 };

 extern int phm_disable_clock_power_gatings(struct pp_hwmgr *hwmgr);
--
1.9.1

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