On Thu, Jan 4, 2018 at 1:01 AM, Rex Zhu <Rex.Zhu at amd.com> wrote:
> v2: add table length check.
>
> DC component expect PP to give max engine clock and
> memory clock through pp_get_display_mode_validation_clocks
> on DGPU as well.
>
> This patch can fix MultiGPU-Display blank
> out with 1 IGPU-4k display and 2 DGPU-two 4K
> displays.
>
> Change-Id: I20454060ebe01955c5653de037dd8c09a576026a
> Signed-off-by: Rex Zhu <Rex.Zhu at amd.com>
> ---
> drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 21 +++++++++++++++++++++
> 1 file changed, 21 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> index 444cc35..f4ada46 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> @@ -4667,6 +4667,26 @@ static int smu7_notify_cac_buffer_info(struct pp_hwmgr *hwmgr,
> return 0;
> }
>
> +static int smu7_get_max_high_clocks(struct pp_hwmgr *hwmgr,
> + struct amd_pp_simple_clock_info *clocks)
> +{
> + struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
> + struct smu7_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table);
> + struct smu7_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table);
> +
> + if (clocks == NULL)
Is it possible that data or sclk or mclk table could be null here?
With that addressed:
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
Looks like vega10 is also missing this callback.
Alex
> + return -EINVAL;
> +
> + clocks->memory_max_clock = mclk_table->count > 1 ?
> + mclk_table->dpm_levels[mclk_table->count-1].value :
> + mclk_table->dpm_levels[0].value;
> + clocks->engine_max_clock = sclk_table->count > 1 ?
> + sclk_table->dpm_levels[sclk_table->count-1].value :
> + sclk_table->dpm_levels[0].value;
> +
> + return 0;
> +}
> +
> static const struct pp_hwmgr_func smu7_hwmgr_funcs = {
> .backend_init = &smu7_hwmgr_backend_init,
> .backend_fini = &smu7_hwmgr_backend_fini,
> @@ -4719,6 +4739,7 @@ static int smu7_notify_cac_buffer_info(struct pp_hwmgr *hwmgr,
> .disable_smc_firmware_ctf = smu7_thermal_disable_alert,
> .start_thermal_controller = smu7_start_thermal_controller,
> .notify_cac_buffer_info = smu7_notify_cac_buffer_info,
> + .get_max_high_clocks = smu7_get_max_high_clocks,
> };
>
> uint8_t smu7_get_sleep_divider_id_from_clock(uint32_t clock,
> --
> 1.9.1
>
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