On Mon, Sep 25, 2017 at 9:49 AM, Rex Zhu <Rex.Zhu at amd.com> wrote:
> Change-Id: If13500f76da6e42f50d40fc794fc5e1e5dc143bf
> Signed-off-by: Rex Zhu <Rex.Zhu at amd.com>
Series is:
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
> ---
> drivers/gpu/drm/amd/include/amd_shared.h | 38 +++++++++++++++++++++++++++-----
> 1 file changed, 33 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/include/amd_shared.h b/drivers/gpu/drm/amd/include/amd_shared.h
> index 292f602..89ad5bf 100644
> --- a/drivers/gpu/drm/amd/include/amd_shared.h
> +++ b/drivers/gpu/drm/amd/include/amd_shared.h
> @@ -232,9 +232,18 @@ struct amd_ip_funcs {
> void (*get_clockgating_state)(void *handle, u32 *flags);
> };
>
> -enum amd_pp_task;
>
> +enum amd_pp_task;
> +enum amd_pp_clock_type;
> struct pp_states_info;
> +struct amd_pp_simple_clock_info;
> +struct amd_pp_display_configuration;
> +struct amd_pp_clock_info;
> +struct pp_display_clock_request;
> +struct pp_wm_sets_with_clock_ranges_soc15;
> +struct pp_clock_levels_with_voltage;
> +struct pp_clock_levels_with_latency;
> +struct amd_pp_clocks;
>
> struct amd_pm_funcs {
> /* export for dpm on ci and si */
> @@ -258,17 +267,13 @@ struct amd_pm_funcs {
> int (*force_clock_level)(void *handle, enum pp_clock_type type, uint32_t mask);
> int (*print_clock_levels)(void *handle, enum pp_clock_type type, char *buf);
> int (*force_performance_level)(void *handle, enum amd_dpm_forced_level level);
> -
> int (*get_sclk_od)(void *handle);
> int (*set_sclk_od)(void *handle, uint32_t value);
> int (*get_mclk_od)(void *handle);
> int (*set_mclk_od)(void *handle, uint32_t value);
> -
> int (*read_sensor)(void *handle, int idx, void *value, int *size);
> -
> enum amd_dpm_forced_level (*get_performance_level)(void *handle);
> enum amd_pm_state_type (*get_current_power_state)(void *handle);
> -
> int (*get_fan_speed_rpm)(void *handle, uint32_t *rpm);
> int (*get_pp_num_states)(void *handle, struct pp_states_info *data);
> int (*get_pp_table)(void *handle, char **table);
> @@ -283,6 +288,7 @@ struct amd_pm_funcs {
> struct amd_pp_profile *request);
> int (*switch_power_profile)(void *handle,
> enum amd_pp_profile_type type);
> +
> /* export for amdgpu */
> void (*powergate_uvd)(void *handle, bool gate);
> void (*powergate_vce)(void *handle, bool gate);
> @@ -291,9 +297,31 @@ struct amd_pm_funcs {
> void *input, void *output);
> int (*load_firmware)(void *handle);
> int (*wait_for_fw_loading_complete)(void *handle);
> + int (*set_clockgating_by_smu)(void *handle, uint32_t msg_id);
> /* export for DISPLAY */
> u32 (*get_sclk)(void *handle, bool low);
> u32 (*get_mclk)(void *handle, bool low);
> + int (*display_configuration_change)(void *handle,
> + const struct amd_pp_display_configuration *input);
> + int (*get_display_power_level)(void *handle,
> + struct amd_pp_simple_clock_info *output);
> + int (*get_current_clocks)(void *handle,
> + struct amd_pp_clock_info *clocks);
> + int (*get_clock_by_type)(void *handle,
> + enum amd_pp_clock_type type,
> + struct amd_pp_clocks *clocks);
> + int (*get_clock_by_type_with_latency)(void *handle,
> + enum amd_pp_clock_type type,
> + struct pp_clock_levels_with_latency *clocks);
> + int (*get_clock_by_type_with_voltage)(void *handle,
> + enum amd_pp_clock_type type,
> + struct pp_clock_levels_with_voltage *clocks);
> + int (*set_watermarks_for_clocks_ranges)(void *handle,
> + struct pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges);
> + int (*display_clock_voltage_request)(void *handle,
> + struct pp_display_clock_request *clock);
> + int (*get_display_mode_validation_clocks)(void *handle,
> + struct amd_pp_simple_clock_info *clocks);
> };
>
>
> --
> 1.9.1
>
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