> -----Original Message----- > From: amd-gfx [mailto:amd-gfx-bounces at lists.freedesktop.org] On Behalf > Of Rex Zhu > Sent: Tuesday, September 26, 2017 1:49 AM > To: amd-gfx at lists.freedesktop.org > Cc: Zhu, Rex > Subject: [PATCH] drm/amd/powerplay: move set_clockgating_by_smu to pp > func table > > Change-Id: I08f7eb9af1ddf4fac199d712f41b9afee94b9acd > Signed-off-by: Rex Zhu <Rex.Zhu at amd.com> Reviewed-by: Alex Deucher <alexander.deucher at amd.com> > --- > drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h | 4 +++ > drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 23 +++++++----- > drivers/gpu/drm/amd/amdgpu/vi.c | 22 +++++++----- > drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 44 +++++++++++--- > --------- > drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h | 1 - > 5 files changed, 54 insertions(+), 40 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h > b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h > index 0d22259..56caaee 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h > @@ -356,6 +356,10 @@ enum amdgpu_pcie_gen { > ((adev)->powerplay.pp_funcs->switch_power_profile(\ > (adev)->powerplay.pp_handle, type)) > > +#define amdgpu_dpm_set_clockgating_by_smu(adev, msg_id) \ > + ((adev)->powerplay.pp_funcs->set_clockgating_by_smu(\ > + (adev)->powerplay.pp_handle, msg_id)) > + > struct amdgpu_dpm { > struct amdgpu_ps *ps; > /* number of valid power states */ > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c > b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c > index e04de7a..2902cec 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c > @@ -5984,7 +5984,6 @@ static int > gfx_v8_0_tonga_update_gfx_clock_gating(struct amdgpu_device *adev, > { > uint32_t msg_id, pp_state = 0; > uint32_t pp_support_state = 0; > - void *pp_handle = adev->powerplay.pp_handle; > > if (adev->cg_flags & (AMD_CG_SUPPORT_GFX_CGCG | > AMD_CG_SUPPORT_GFX_CGLS)) { > if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) { > @@ -6002,7 +6001,8 @@ static int > gfx_v8_0_tonga_update_gfx_clock_gating(struct amdgpu_device *adev, > PP_BLOCK_GFX_CG, > pp_support_state, > pp_state); > - amd_set_clockgating_by_smu(pp_handle, msg_id); > + if (adev->powerplay.pp_funcs->set_clockgating_by_smu) > + amdgpu_dpm_set_clockgating_by_smu(adev, > msg_id); > } > > if (adev->cg_flags & (AMD_CG_SUPPORT_GFX_MGCG | > AMD_CG_SUPPORT_GFX_MGLS)) { > @@ -6023,7 +6023,8 @@ static int > gfx_v8_0_tonga_update_gfx_clock_gating(struct amdgpu_device *adev, > PP_BLOCK_GFX_MG, > pp_support_state, > pp_state); > - amd_set_clockgating_by_smu(pp_handle, msg_id); > + if (adev->powerplay.pp_funcs->set_clockgating_by_smu) > + amdgpu_dpm_set_clockgating_by_smu(adev, > msg_id); > } > > return 0; > @@ -6035,7 +6036,6 @@ static int > gfx_v8_0_polaris_update_gfx_clock_gating(struct amdgpu_device *adev, > > uint32_t msg_id, pp_state = 0; > uint32_t pp_support_state = 0; > - void *pp_handle = adev->powerplay.pp_handle; > > if (adev->cg_flags & (AMD_CG_SUPPORT_GFX_CGCG | > AMD_CG_SUPPORT_GFX_CGLS)) { > if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) { > @@ -6053,7 +6053,8 @@ static int > gfx_v8_0_polaris_update_gfx_clock_gating(struct amdgpu_device *adev, > PP_BLOCK_GFX_CG, > pp_support_state, > pp_state); > - amd_set_clockgating_by_smu(pp_handle, msg_id); > + if (adev->powerplay.pp_funcs->set_clockgating_by_smu) > + amdgpu_dpm_set_clockgating_by_smu(adev, > msg_id); > } > > if (adev->cg_flags & (AMD_CG_SUPPORT_GFX_3D_CGCG | > AMD_CG_SUPPORT_GFX_3D_CGLS)) { > @@ -6072,7 +6073,8 @@ static int > gfx_v8_0_polaris_update_gfx_clock_gating(struct amdgpu_device *adev, > PP_BLOCK_GFX_3D, > pp_support_state, > pp_state); > - amd_set_clockgating_by_smu(pp_handle, msg_id); > + if (adev->powerplay.pp_funcs->set_clockgating_by_smu) > + amdgpu_dpm_set_clockgating_by_smu(adev, > msg_id); > } > > if (adev->cg_flags & (AMD_CG_SUPPORT_GFX_MGCG | > AMD_CG_SUPPORT_GFX_MGLS)) { > @@ -6093,7 +6095,8 @@ static int > gfx_v8_0_polaris_update_gfx_clock_gating(struct amdgpu_device *adev, > PP_BLOCK_GFX_MG, > pp_support_state, > pp_state); > - amd_set_clockgating_by_smu(pp_handle, msg_id); > + if (adev->powerplay.pp_funcs->set_clockgating_by_smu) > + amdgpu_dpm_set_clockgating_by_smu(adev, > msg_id); > } > > if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) { > @@ -6108,7 +6111,8 @@ static int > gfx_v8_0_polaris_update_gfx_clock_gating(struct amdgpu_device *adev, > PP_BLOCK_GFX_RLC, > pp_support_state, > pp_state); > - amd_set_clockgating_by_smu(pp_handle, msg_id); > + if (adev->powerplay.pp_funcs->set_clockgating_by_smu) > + amdgpu_dpm_set_clockgating_by_smu(adev, > msg_id); > } > > if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) { > @@ -6122,7 +6126,8 @@ static int > gfx_v8_0_polaris_update_gfx_clock_gating(struct amdgpu_device *adev, > PP_BLOCK_GFX_CP, > pp_support_state, > pp_state); > - amd_set_clockgating_by_smu(pp_handle, msg_id); > + if (adev->powerplay.pp_funcs->set_clockgating_by_smu) > + amdgpu_dpm_set_clockgating_by_smu(adev, > msg_id); > } > > return 0; > diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c > b/drivers/gpu/drm/amd/amdgpu/vi.c > index 2ac5b84..3a4c2fa 100644 > --- a/drivers/gpu/drm/amd/amdgpu/vi.c > +++ b/drivers/gpu/drm/amd/amdgpu/vi.c > @@ -1255,7 +1255,6 @@ static int > vi_common_set_clockgating_state_by_smu(void *handle, > uint32_t msg_id, pp_state = 0; > uint32_t pp_support_state = 0; > struct amdgpu_device *adev = (struct amdgpu_device *)handle; > - void *pp_handle = adev->powerplay.pp_handle; > > if (adev->cg_flags & (AMD_CG_SUPPORT_MC_LS | > AMD_CG_SUPPORT_MC_MGCG)) { > if (adev->cg_flags & AMD_CG_SUPPORT_MC_LS) { > @@ -1272,7 +1271,8 @@ static int > vi_common_set_clockgating_state_by_smu(void *handle, > PP_BLOCK_SYS_MC, > pp_support_state, > pp_state); > - amd_set_clockgating_by_smu(pp_handle, msg_id); > + if (adev->powerplay.pp_funcs->set_clockgating_by_smu) > + amdgpu_dpm_set_clockgating_by_smu(adev, > msg_id); > } > > if (adev->cg_flags & (AMD_CG_SUPPORT_SDMA_LS | > AMD_CG_SUPPORT_SDMA_MGCG)) { > @@ -1290,7 +1290,8 @@ static int > vi_common_set_clockgating_state_by_smu(void *handle, > PP_BLOCK_SYS_SDMA, > pp_support_state, > pp_state); > - amd_set_clockgating_by_smu(pp_handle, msg_id); > + if (adev->powerplay.pp_funcs->set_clockgating_by_smu) > + amdgpu_dpm_set_clockgating_by_smu(adev, > msg_id); > } > > if (adev->cg_flags & (AMD_CG_SUPPORT_HDP_LS | > AMD_CG_SUPPORT_HDP_MGCG)) { > @@ -1308,7 +1309,8 @@ static int > vi_common_set_clockgating_state_by_smu(void *handle, > PP_BLOCK_SYS_HDP, > pp_support_state, > pp_state); > - amd_set_clockgating_by_smu(pp_handle, msg_id); > + if (adev->powerplay.pp_funcs->set_clockgating_by_smu) > + amdgpu_dpm_set_clockgating_by_smu(adev, > msg_id); > } > > > @@ -1322,7 +1324,8 @@ static int > vi_common_set_clockgating_state_by_smu(void *handle, > PP_BLOCK_SYS_BIF, > PP_STATE_SUPPORT_LS, > pp_state); > - amd_set_clockgating_by_smu(pp_handle, msg_id); > + if (adev->powerplay.pp_funcs->set_clockgating_by_smu) > + amdgpu_dpm_set_clockgating_by_smu(adev, > msg_id); > } > if (adev->cg_flags & AMD_CG_SUPPORT_BIF_MGCG) { > if (state == AMD_CG_STATE_UNGATE) > @@ -1334,7 +1337,8 @@ static int > vi_common_set_clockgating_state_by_smu(void *handle, > PP_BLOCK_SYS_BIF, > PP_STATE_SUPPORT_CG, > pp_state); > - amd_set_clockgating_by_smu(pp_handle, msg_id); > + if (adev->powerplay.pp_funcs->set_clockgating_by_smu) > + amdgpu_dpm_set_clockgating_by_smu(adev, > msg_id); > } > > if (adev->cg_flags & AMD_CG_SUPPORT_DRM_LS) { > @@ -1348,7 +1352,8 @@ static int > vi_common_set_clockgating_state_by_smu(void *handle, > PP_BLOCK_SYS_DRM, > PP_STATE_SUPPORT_LS, > pp_state); > - amd_set_clockgating_by_smu(pp_handle, msg_id); > + if (adev->powerplay.pp_funcs->set_clockgating_by_smu) > + amdgpu_dpm_set_clockgating_by_smu(adev, > msg_id); > } > > if (adev->cg_flags & AMD_CG_SUPPORT_ROM_MGCG) { > @@ -1362,7 +1367,8 @@ static int > vi_common_set_clockgating_state_by_smu(void *handle, > PP_BLOCK_SYS_ROM, > PP_STATE_SUPPORT_CG, > pp_state); > - amd_set_clockgating_by_smu(pp_handle, msg_id); > + if (adev->powerplay.pp_funcs->set_clockgating_by_smu) > + amdgpu_dpm_set_clockgating_by_smu(adev, > msg_id); > } > return 0; > } > diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c > b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c > index f475438..6354ac9 100644 > --- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c > +++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c > @@ -210,28 +210,6 @@ static int pp_sw_reset(void *handle) > return 0; > } > > - > -int amd_set_clockgating_by_smu(void *handle, uint32_t msg_id) > -{ > - struct pp_hwmgr *hwmgr; > - struct pp_instance *pp_handle = (struct pp_instance *)handle; > - int ret = 0; > - > - ret = pp_check(pp_handle); > - > - if (ret) > - return ret; > - > - hwmgr = pp_handle->hwmgr; > - > - if (hwmgr->hwmgr_func->update_clock_gatings == NULL) { > - pr_info("%s was not implemented.\n", __func__); > - return 0; > - } > - > - return hwmgr->hwmgr_func->update_clock_gatings(hwmgr, > &msg_id); > -} > - > static int pp_set_powergating_state(void *handle, > enum amd_powergating_state state) > { > @@ -327,6 +305,27 @@ static int pp_dpm_fw_loading_complete(void > *handle) > return 0; > } > > +static int pp_set_clockgating_by_smu(void *handle, uint32_t msg_id) > +{ > + struct pp_hwmgr *hwmgr; > + struct pp_instance *pp_handle = (struct pp_instance *)handle; > + int ret = 0; > + > + ret = pp_check(pp_handle); > + > + if (ret) > + return ret; > + > + hwmgr = pp_handle->hwmgr; > + > + if (hwmgr->hwmgr_func->update_clock_gatings == NULL) { > + pr_info("%s was not implemented.\n", __func__); > + return 0; > + } > + > + return hwmgr->hwmgr_func->update_clock_gatings(hwmgr, > &msg_id); > +} > + > static void pp_dpm_en_umd_pstate(struct pp_hwmgr *hwmgr, > enum > amd_dpm_forced_level *level) > { > @@ -1166,6 +1165,7 @@ static int pp_dpm_switch_power_profile(void > *handle, > .get_power_profile_state = pp_dpm_get_power_profile_state, > .set_power_profile_state = pp_dpm_set_power_profile_state, > .switch_power_profile = pp_dpm_switch_power_profile, > + .set_clockgating_by_smu = pp_set_clockgating_by_smu, > }; > > int amd_powerplay_reset(void *handle) > diff --git a/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h > b/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h > index e52adc8..95932cc 100644 > --- a/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h > +++ b/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h > @@ -304,6 +304,5 @@ int > amd_powerplay_display_clock_voltage_request(void *handle, > int amd_powerplay_get_display_mode_validation_clocks(void *handle, > struct amd_pp_simple_clock_info *output); > > -int amd_set_clockgating_by_smu(void *handle, uint32_t msg_id); > > #endif /* _AMD_POWERPLAY_H_ */ > -- > 1.9.1 > > _______________________________________________ > amd-gfx mailing list > amd-gfx at lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx
