RB: Xiangliang Yu <Xiangliang.Yu at amd.com> -----Original Message----- From: Ding, Pixel Sent: Monday, September 25, 2017 2:42 PM To: Liu, Monk <Monk.Liu at amd.com>; amd-gfx at lists.freedesktop.org; Min, Frank <Frank.Min at amd.com>; Deucher, Alexander <Alexander.Deucher at amd.com>; Yu, Xiangliang <Xiangliang.Yu at amd.com> Subject: Re: [PATCH] drm/amdgpu: right shift 2 bits for SDMA_GFX_RB_WPTR_POLL_ADDR_LO Hi Monk, The world switch gets immediately fail. According to Xiangliangâ??s comment, I think 17.50 also has this issue. Other G branch uses original patch from Frank, that doesnâ??t have this issue. Please confirm this. Also refer to http://adcweb02.amd.com/orlvalid/regspec/web_regspec/vega11/regspec/vega11_chip/public/index.html SDMA0_GFX_RB_WPTR_POLL_ADDR_LO ADDR 31:2 I update a v2 patch for this. I think it must fail if you really overwrite the address to 31:0. â?? Sincerely Yours, Pixel On 25/09/2017, 2:37 PM, "Liu, Monk" <Monk.Liu at amd.com> wrote: >Hold on, > >We didn't hit test fail without your patch, actually at least VEGA10 doesn't have the issue you mentioned, >Can you elaborate what issue or test case you can fix with this patch ? >Besides, please don't change anything on vega10 before you verified it > >BR Monk > >-----Original Message----- >From: Pixel Ding [mailto:Pixel.Ding at amd.com] >Sent: Monday, September 25, 2017 2:16 PM >To: amd-gfx at lists.freedesktop.org; Ding, Pixel <Pixel.Ding at amd.com>; Min, Frank <Frank.Min at amd.com>; Liu, Monk <Monk.Liu at amd.com>; Deucher, Alexander <Alexander.Deucher at amd.com> >Subject: [PATCH] drm/amdgpu: right shift 2 bits for SDMA_GFX_RB_WPTR_POLL_ADDR_LO > >Both Tonga and Vega register SPECs indicate that this registers only use 31:2 bits in DW. SRIOV test case immediately fails withtout this shift. > >Signed-off-by: Pixel Ding <Pixel.Ding at amd.com> >--- > drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 2 +- drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 2 +- > 2 files changed, 2 insertions(+), 2 deletions(-) > >diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c >index 72f31cc..947f019 100644 >--- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c >+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c >@@ -714,7 +714,7 @@ static int sdma_v3_0_gfx_resume(struct amdgpu_device *adev) > wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); > > WREG32(mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO + sdma_offsets[i], >- lower_32_bits(wptr_gpu_addr)); >+ lower_32_bits(wptr_gpu_addr) >> 2); > WREG32(mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI + sdma_offsets[i], > upper_32_bits(wptr_gpu_addr)); > wptr_poll_cntl = RREG32(mmSDMA0_GFX_RB_WPTR_POLL_CNTL + sdma_offsets[i]); diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c >index c26d205..26d7f03 100644 >--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c >+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c >@@ -665,7 +665,7 @@ static int sdma_v4_0_gfx_resume(struct amdgpu_device *adev) > /* setup the wptr shadow polling */ > wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4); > WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO), >- lower_32_bits(wptr_gpu_addr)); >+ lower_32_bits(wptr_gpu_addr) >> 2); > WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI), > upper_32_bits(wptr_gpu_addr)); > wptr_poll_cntl = RREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL)); >-- >2.7.4 >
