Got some feedback from Dave, and this patch doesn't handle dri3 use
cases correctly.
Regards,
Andres
On 2017-09-18 07:16 PM, Andres Rodriguez wrote:
> Implicit sync kicks in when a buffer is used by two different amdgpu
> contexts simultaneously. Jobs that use explicit synchronization
> mechanisms end up needlessly waiting to be scheduled for long periods
> of time in order to achieve serialized execution.
>
> This patch disables implicit synchronization for all radv allocations.
> The only systems that require implicit synchronization are DRI2/3 and
> PRIME.
>
> Signed-off-by: Andres Rodriguez <andresx7 at gmail.com>
> ---
> src/amd/vulkan/winsys/amdgpu/radv_amdgpu_bo.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_bo.c b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_bo.c
> index 325f875..9dc7559 100644
> --- a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_bo.c
> +++ b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_bo.c
> @@ -330,6 +330,7 @@ radv_amdgpu_winsys_bo_create(struct radeon_winsys *_ws,
> request.flags |= AMDGPU_GEM_CREATE_NO_CPU_ACCESS;
> if (flags & RADEON_FLAG_GTT_WC)
> request.flags |= AMDGPU_GEM_CREATE_CPU_GTT_USWC;
> + request.flags |= AMDGPU_GEM_CREATE_EXPLICIT_SYNC;
>
> r = amdgpu_bo_alloc(ws->dev, &request, &buf_handle);
> if (r) {
