Patch 1, 3 are Reviewed-by: Huang Rui <ray.huang at amd.com>
With minor comments on Patch 2 and 4, with that fixed, please feel free to
add Reviewed-by: Huang Rui <ray.huang at amd.com>
Thanks,
Rui
On Mon, Sep 11, 2017 at 09:22:02AM +0800, Evan Quan wrote:
> Change-Id: I9b7ebc99b7c75c03fb46d16c4c49348dd551325e
> Signed-off-by: Evan Quan <evan.quan at amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/psp_v10_0.c | 16 +++++++++-------
> 1 file changed, 9 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
> index 5283113..702d68d 100644
> --- a/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/psp_v10_0.c
> @@ -137,15 +137,13 @@ int psp_v10_0_prep_cmd_buf(struct amdgpu_firmware_info *ucode, struct psp_gfx_cm
> {
> int ret;
> uint64_t fw_mem_mc_addr = ucode->mc_addr;
> - struct common_firmware_header *header;
>
> memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp));
> - header = (struct common_firmware_header *)ucode->fw;
>
> cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW;
> cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr);
> cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr);
> - cmd->cmd.cmd_load_ip_fw.fw_size = le32_to_cpu(header->ucode_size_bytes);
> + cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size;
>
> ret = psp_v10_0_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type);
> if (ret)
> @@ -246,15 +244,20 @@ int psp_v10_0_cmd_submit(struct psp_context *psp,
> struct psp_gfx_rb_frame * write_frame = psp->km_ring.ring_mem;
> struct psp_ring *ring = &psp->km_ring;
> struct amdgpu_device *adev = psp->adev;
> + uint32_t ring_size_dw = ring->ring_size / 4;
> + uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4;
>
> /* KM (GPCOM) prepare write pointer */
> psp_write_ptr_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67);
>
> /* Update KM RB frame pointer to new frame */
> - if ((psp_write_ptr_reg % ring->ring_size) == 0)
> + if ((psp_write_ptr_reg % ring_size_dw) == 0)
> write_frame = ring->ring_mem;
> else
> - write_frame = ring->ring_mem + (psp_write_ptr_reg / (sizeof(struct psp_gfx_rb_frame) / 4));
> + write_frame = ring->ring_mem + (psp_write_ptr_reg / rb_frame_size_dw);
> +
> + /* Initialize KM RB frame */
> + memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame));
>
> /* Update KM RB frame */
> write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr);
> @@ -264,8 +267,7 @@ int psp_v10_0_cmd_submit(struct psp_context *psp,
> write_frame->fence_value = index;
>
> /* Update the write Pointer in DWORDs */
> - psp_write_ptr_reg += sizeof(struct psp_gfx_rb_frame) / 4;
> - psp_write_ptr_reg = (psp_write_ptr_reg >= ring->ring_size) ? 0 : psp_write_ptr_reg;
> + psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw;
> WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, psp_write_ptr_reg);
>
> return 0;
> --
> 2.7.4
>
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> amd-gfx at lists.freedesktop.org
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