Yes. Best Regards Rex -----Original Message----- From: amd-gfx [mailto:amd-gfx-bounces@xxxxxxxxxxxxxxxxxxxxx] On Behalf Of Tom St Denis Sent: Wednesday, September 06, 2017 12:23 AM To: amd-gfx at lists.freedesktop.org Subject: Re: unclear code in vega10 pp After seeing this style a few other places in the same file are they just padding out the rest of the array with the highest setting? Tom On 05/09/17 12:18 PM, Tom St Denis wrote: > In vega10_populate_smc_link_levels(): there's this bit > > Â Â Â Â j = i - 1; > Â Â Â Â while (i < NUM_LINK_LEVELS) { > Â Â Â Â Â Â Â pp_table->PcieGenSpeed[i] = pcie_table->pcie_gen[j]; > Â Â Â Â Â Â Â pp_table->PcieLaneCount[i] = pcie_table->pcie_lane[j]; > > Â Â Â Â Â Â Â result = vega10_populate_single_lclk_level(hwmgr, > Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â pcie_table->lclk[j], &(pp_table->LclkDid[i])); > Â Â Â Â Â Â Â if (result) { > Â Â Â Â Â Â Â Â Â Â Â pr_info("Populate LClock Level %d Failed!\n", i); > Â Â Â Â Â Â Â Â Â Â Â return result; > Â Â Â Â Â Â Â } > Â Â Â Â Â Â Â i++; > Â Â Â Â } > > It seems 'j' isn't changing so it's spamming multiple entries in the > lclkdid[] array based on the same entries from the pcie_table->pcie*[j]. > > Is that intentional or is a ++ or -- to j missing? > > Cheers, > Tom > _______________________________________________ > amd-gfx mailing list > amd-gfx at lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx _______________________________________________ amd-gfx mailing list amd-gfx at lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
