[PATCH 19/20] drm/amd/display: change dml numdpp var to uint

[harry.wentland@xxxxxxx (Harry Wentland)]

From: Dmytro Laktyushkin <Dmytro.Laktyushkin@xxxxxxx>

Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin at amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng at amd.com>
Acked-by: Harry Wentland <Harry.Wentland at amd.com>
---
 drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c | 14 +++++++-------
 drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h |  2 +-
 2 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
index 117ec11ef304..ffd1d8d10bdf 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
@@ -1158,7 +1158,7 @@ static bool CalculatePrefetchSchedule(
 		else if (PageTableLevels == 3)
 			*Tno_bw = UrgentExtraLatency;
 		else
-			Tno_bw = 0;
+			*Tno_bw = 0;
 	} else if (DCCEnable)
 		*Tno_bw = LineTime;
 	else
@@ -4721,14 +4721,14 @@ static void ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_
 					&& mode_lib->vba.SwathWidthYSingleDPP[k]
 							<= mode_lib->vba.MaximumSwathWidth[k]
 					&& mode_lib->vba.ODMCombineEnablePerState[i][k] == false) {
-				mode_lib->vba.NoOfDPP[i][k] = 1.0;
+				mode_lib->vba.NoOfDPP[i][k] = 1;
 				mode_lib->vba.RequiredDPPCLK[i][k] =
 						mode_lib->vba.MinDPPCLKUsingSingleDPP[k]
 								* (1.0
 										+ mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading
 												/ 100.0);
 			} else {
-				mode_lib->vba.NoOfDPP[i][k] = 2.0;
+				mode_lib->vba.NoOfDPP[i][k] = 2;
 				mode_lib->vba.RequiredDPPCLK[i][k] =
 						mode_lib->vba.MinDPPCLKUsingSingleDPP[k]
 								* (1.0
@@ -4790,14 +4790,14 @@ static void ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_
 								<= mode_lib->vba.MaximumSwathWidth[k]
 						&& mode_lib->vba.ODMCombineEnablePerState[i][k]
 								== false) {
-					mode_lib->vba.NoOfDPP[i][k] = 1.0;
+					mode_lib->vba.NoOfDPP[i][k] = 1;
 					mode_lib->vba.RequiredDPPCLK[i][k] =
 							mode_lib->vba.MinDPPCLKUsingSingleDPP[k]
 									* (1.0
 											+ mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading
 													/ 100.0);
 				} else {
-					mode_lib->vba.NoOfDPP[i][k] = 2.0;
+					mode_lib->vba.NoOfDPP[i][k] = 2;
 					mode_lib->vba.RequiredDPPCLK[i][k] =
 							mode_lib->vba.MinDPPCLKUsingSingleDPP[k]
 									* (1.0
@@ -4833,14 +4833,14 @@ static void ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_
 				mode_lib->vba.ODMCombineEnablePerState[i][k] = false;
 				if (mode_lib->vba.SwathWidthYSingleDPP[k]
 						<= mode_lib->vba.MaximumSwathWidth[k]) {
-					mode_lib->vba.NoOfDPP[i][k] = 1.0;
+					mode_lib->vba.NoOfDPP[i][k] = 1;
 					mode_lib->vba.RequiredDPPCLK[i][k] =
 							mode_lib->vba.MinDPPCLKUsingSingleDPP[k]
 									* (1.0
 											+ mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading
 													/ 100.0);
 				} else {
-					mode_lib->vba.NoOfDPP[i][k] = 2.0;
+					mode_lib->vba.NoOfDPP[i][k] = 2;
 					mode_lib->vba.RequiredDPPCLK[i][k] =
 							mode_lib->vba.MinDPPCLKUsingSingleDPP[k]
 									* (1.0
diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
index 63ad4a7bfeb5..4b8c1b911f17 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
@@ -489,7 +489,7 @@ struct vba_vars_st {
 	double CursorBufferSize;
 	double CursorChunkSize;
 	unsigned int Mode;
-	double NoOfDPP[DC__VOLTAGE_STATES + 1][DC__NUM_DPP__MAX];
+	unsigned int NoOfDPP[DC__VOLTAGE_STATES + 1][DC__NUM_DPP__MAX];
 	double OutputLinkDPLanes[DC__NUM_DPP__MAX];
 	double SwathWidthYPerState[DC__VOLTAGE_STATES + 1][DC__NUM_DPP__MAX];
 	double SwathHeightYPerState[DC__VOLTAGE_STATES + 1][DC__NUM_DPP__MAX];
-- 
2.14.1