To avoid duplication of header files,amd/include/asic_reg/vega10 will be removed. Header files under this folder will be moved to corresponding ip folders within asic_reg/. Also removed some unused header files of vega10. https://lists.freedesktop.org/archives/amd-gfx/2017-November/016191.html Included above thread in this patch-set as they are all cleaning up vega10 header files. Patches are formated with flag --find-renames and --irreversible-delete. This will omit the preimage for delete and renames. But resulting patches are just for reviewing and not meant to be applied with git apply. Feifei Xu (16): drm/amd/include:cleanup vega10 sdma0/1 header files. drm/amd/include:cleanup vega10 hdp header files. drm/amd/include:cleanup vega10 mp header files. drm/amd/include:cleanup vega10 athub header files. drm/amd/include:cleanup vega10 thm header files. drm/amd/include: cleanup vega10 umc header files. drm/amd/include:cleanup vega10 dce header files. drm/amd/include:cleanup vega10 uvd header files. drm/amd/include:cleanup vega10 vce header files. drm/amd/include:cleanup vega10 gc header files. drm/amd/include:cleanup vega10 mmhub header files. drm/amd/include:cleanup vega10 nbio header files. drm/amd/include:cleanup vega10 nbif header files. drm/amd/include:cleanup vega10 smuio header files. drm/amd/include:cleanup vega10 osssys header files. drm/amd/include:cleanup vega10 header files. drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 2 +- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 10 +- drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c | 10 +- drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 20 +- drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c | 15 +- drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c | 10 +- drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c | 10 +- drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c | 4 +- drivers/gpu/drm/amd/amdgpu/psp_v10_0.c | 2 +- drivers/gpu/drm/amd/amdgpu/psp_v3_1.c | 12 +- drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 16 +- drivers/gpu/drm/amd/amdgpu/soc15.c | 24 +- drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c | 20 +- drivers/gpu/drm/amd/amdgpu/vce_v4_0.c | 12 +- drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 4 +- drivers/gpu/drm/amd/amdgpu/vega10_ih.c | 6 +- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +- .../amd/display/dc/dce120/dce120_hw_sequencer.c | 6 +- .../drm/amd/display/dc/dce120/dce120_resource.c | 8 +- .../display/dc/dce120/dce120_timing_generator.c | 6 +- .../gpu/drm/amd/display/dc/dcn10/dcn10_resource.c | 2 +- .../amd/display/dc/gpio/dce120/hw_factory_dce120.c | 6 +- .../display/dc/gpio/dce120/hw_translate_dce120.c | 6 +- .../amd/display/dc/gpio/dcn10/hw_factory_dcn10.c | 2 +- .../amd/display/dc/gpio/dcn10/hw_translate_dcn10.c | 2 +- .../amd/display/dc/i2caux/dce120/i2caux_dce120.c | 6 +- .../drm/amd/display/dc/i2caux/dcn10/i2caux_dcn10.c | 2 +- .../amd/display/dc/irq/dce120/irq_service_dce120.c | 6 +- .../amd/display/dc/irq/dcn10/irq_service_dcn10.c | 2 +- .../amd/include/asic_reg/athub/athub_1_0_offset.h | 453 + .../amd/include/asic_reg/athub/athub_1_0_sh_mask.h | 2045 ++++ .../asic_reg/{vega10/DC => dce}/dce_12_0_offset.h | 0 .../asic_reg/{vega10/DC => dce}/dce_12_0_sh_mask.h | 0 .../asic_reg/{vega10/GC => gc}/gc_9_0_default.h | 0 .../asic_reg/{vega10/GC => gc}/gc_9_0_offset.h | 0 .../asic_reg/{vega10/GC => gc}/gc_9_0_sh_mask.h | 0 .../drm/amd/include/asic_reg/hdp/hdp_4_0_offset.h | 209 + .../drm/amd/include/asic_reg/hdp/hdp_4_0_sh_mask.h | 601 ++ .../{vega10/MMHUB => mmhub}/mmhub_1_0_default.h | 0 .../{vega10/MMHUB => mmhub}/mmhub_1_0_offset.h | 0 .../{vega10/MMHUB => mmhub}/mmhub_1_0_sh_mask.h | 0 .../drm/amd/include/asic_reg/mp/mp_9_0_offset.h | 375 + .../drm/amd/include/asic_reg/mp/mp_9_0_sh_mask.h | 1463 +++ .../{vega10/NBIF => nbif}/nbif_6_1_offset.h | 0 .../{vega10/NBIF => nbif}/nbif_6_1_sh_mask.h | 0 .../{vega10/NBIO => nbio}/nbio_6_1_default.h | 0 .../{vega10/NBIO => nbio}/nbio_6_1_offset.h | 0 .../{vega10/NBIO => nbio}/nbio_6_1_sh_mask.h | 0 .../{vega10/OSSSYS => oss}/osssys_4_0_offset.h | 0 .../{vega10/OSSSYS => oss}/osssys_4_0_sh_mask.h | 0 .../amd/include/asic_reg/sdma0/sdma0_4_0_default.h | 286 + .../amd/include/asic_reg/sdma0/sdma0_4_0_offset.h | 547 ++ .../amd/include/asic_reg/sdma0/sdma0_4_0_sh_mask.h | 1852 ++++ .../amd/include/asic_reg/sdma1/sdma1_4_0_default.h | 282 + .../amd/include/asic_reg/sdma1/sdma1_4_0_offset.h | 539 ++ .../amd/include/asic_reg/sdma1/sdma1_4_0_sh_mask.h | 1810 ++++ .../{vega10/SMUIO => smuio}/smuio_9_0_offset.h | 0 .../{vega10/SMUIO => smuio}/smuio_9_0_sh_mask.h | 0 .../asic_reg/{vega10/THM => thm}/thm_9_0_default.h | 0 .../asic_reg/{vega10/THM => thm}/thm_9_0_offset.h | 0 .../asic_reg/{vega10/THM => thm}/thm_9_0_sh_mask.h | 0 .../asic_reg/{vega10/UMC => umc}/umc_6_0_default.h | 0 .../asic_reg/{vega10/UMC => umc}/umc_6_0_offset.h | 0 .../asic_reg/{vega10/UMC => umc}/umc_6_0_sh_mask.h | 0 .../asic_reg/{vega10/UVD => uvd}/uvd_7_0_offset.h | 0 .../asic_reg/{vega10/UVD => uvd}/uvd_7_0_sh_mask.h | 0 .../asic_reg/{vega10/VCE => vce}/vce_4_0_default.h | 0 .../asic_reg/{vega10/VCE => vce}/vce_4_0_offset.h | 0 .../asic_reg/{vega10/VCE => vce}/vce_4_0_sh_mask.h | 0 .../asic_reg/vega10/ATHUB/athub_1_0_default.h | 241 - .../asic_reg/vega10/ATHUB/athub_1_0_offset.h | 453 - .../asic_reg/vega10/ATHUB/athub_1_0_sh_mask.h | 2045 ---- .../include/asic_reg/vega10/DC/dce_12_0_default.h | 9868 -------------------- .../include/asic_reg/vega10/HDP/hdp_4_0_default.h | 117 - .../include/asic_reg/vega10/HDP/hdp_4_0_offset.h | 209 - .../include/asic_reg/vega10/HDP/hdp_4_0_sh_mask.h | 601 -- .../include/asic_reg/vega10/MP/mp_9_0_default.h | 342 - .../amd/include/asic_reg/vega10/MP/mp_9_0_offset.h | 375 - .../include/asic_reg/vega10/MP/mp_9_0_sh_mask.h | 1463 --- .../asic_reg/vega10/NBIF/nbif_6_1_default.h | 1271 --- .../asic_reg/vega10/OSSSYS/osssys_4_0_default.h | 176 - .../asic_reg/vega10/SDMA0/sdma0_4_0_default.h | 286 - .../asic_reg/vega10/SDMA0/sdma0_4_0_offset.h | 547 -- .../asic_reg/vega10/SDMA0/sdma0_4_0_sh_mask.h | 1852 ---- .../asic_reg/vega10/SDMA1/sdma1_4_0_default.h | 282 - .../asic_reg/vega10/SDMA1/sdma1_4_0_offset.h | 539 -- .../asic_reg/vega10/SDMA1/sdma1_4_0_sh_mask.h | 1810 ---- .../asic_reg/vega10/SMUIO/smuio_9_0_default.h | 100 - .../include/asic_reg/vega10/UVD/uvd_7_0_default.h | 127 - .../amd/include/{asic_reg/vega10 => }/soc15ip.h | 0 .../include/{asic_reg/vega10 => }/vega10_enum.h | 0 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_inc.h | 23 +- drivers/gpu/drm/amd/powerplay/inc/pp_soc15.h | 2 +- 93 files changed, 10590 insertions(+), 22834 deletions(-) create mode 100644 drivers/gpu/drm/amd/include/asic_reg/athub/athub_1_0_offset.h create mode 100644 drivers/gpu/drm/amd/include/asic_reg/athub/athub_1_0_sh_mask.h rename drivers/gpu/drm/amd/include/asic_reg/{vega10/DC => dce}/dce_12_0_offset.h (100%) rename drivers/gpu/drm/amd/include/asic_reg/{vega10/DC => dce}/dce_12_0_sh_mask.h (100%) rename drivers/gpu/drm/amd/include/asic_reg/{vega10/GC => gc}/gc_9_0_default.h (100%) rename drivers/gpu/drm/amd/include/asic_reg/{vega10/GC => gc}/gc_9_0_offset.h (100%) rename drivers/gpu/drm/amd/include/asic_reg/{vega10/GC => gc}/gc_9_0_sh_mask.h (100%) create mode 100644 drivers/gpu/drm/amd/include/asic_reg/hdp/hdp_4_0_offset.h create mode 100644 drivers/gpu/drm/amd/include/asic_reg/hdp/hdp_4_0_sh_mask.h rename drivers/gpu/drm/amd/include/asic_reg/{vega10/MMHUB => mmhub}/mmhub_1_0_default.h (100%) rename drivers/gpu/drm/amd/include/asic_reg/{vega10/MMHUB => mmhub}/mmhub_1_0_offset.h (100%) rename drivers/gpu/drm/amd/include/asic_reg/{vega10/MMHUB => mmhub}/mmhub_1_0_sh_mask.h (100%) create mode 100644 drivers/gpu/drm/amd/include/asic_reg/mp/mp_9_0_offset.h create mode 100644 drivers/gpu/drm/amd/include/asic_reg/mp/mp_9_0_sh_mask.h rename drivers/gpu/drm/amd/include/asic_reg/{vega10/NBIF => nbif}/nbif_6_1_offset.h (100%) rename drivers/gpu/drm/amd/include/asic_reg/{vega10/NBIF => nbif}/nbif_6_1_sh_mask.h (100%) rename drivers/gpu/drm/amd/include/asic_reg/{vega10/NBIO => nbio}/nbio_6_1_default.h (100%) rename drivers/gpu/drm/amd/include/asic_reg/{vega10/NBIO => nbio}/nbio_6_1_offset.h (100%) rename drivers/gpu/drm/amd/include/asic_reg/{vega10/NBIO => nbio}/nbio_6_1_sh_mask.h (100%) rename drivers/gpu/drm/amd/include/asic_reg/{vega10/OSSSYS => oss}/osssys_4_0_offset.h (100%) rename drivers/gpu/drm/amd/include/asic_reg/{vega10/OSSSYS => oss}/osssys_4_0_sh_mask.h (100%) create mode 100644 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_0_default.h create mode 100644 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_0_offset.h create mode 100644 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_0_sh_mask.h create mode 100644 drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_0_default.h create mode 100644 drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_0_offset.h create mode 100644 drivers/gpu/drm/amd/include/asic_reg/sdma1/sdma1_4_0_sh_mask.h rename drivers/gpu/drm/amd/include/asic_reg/{vega10/SMUIO => smuio}/smuio_9_0_offset.h (100%) rename drivers/gpu/drm/amd/include/asic_reg/{vega10/SMUIO => smuio}/smuio_9_0_sh_mask.h (100%) rename drivers/gpu/drm/amd/include/asic_reg/{vega10/THM => thm}/thm_9_0_default.h (100%) rename drivers/gpu/drm/amd/include/asic_reg/{vega10/THM => thm}/thm_9_0_offset.h (100%) rename drivers/gpu/drm/amd/include/asic_reg/{vega10/THM => thm}/thm_9_0_sh_mask.h (100%) rename drivers/gpu/drm/amd/include/asic_reg/{vega10/UMC => umc}/umc_6_0_default.h (100%) rename drivers/gpu/drm/amd/include/asic_reg/{vega10/UMC => umc}/umc_6_0_offset.h (100%) rename drivers/gpu/drm/amd/include/asic_reg/{vega10/UMC => umc}/umc_6_0_sh_mask.h (100%) rename drivers/gpu/drm/amd/include/asic_reg/{vega10/UVD => uvd}/uvd_7_0_offset.h (100%) rename drivers/gpu/drm/amd/include/asic_reg/{vega10/UVD => uvd}/uvd_7_0_sh_mask.h (100%) rename drivers/gpu/drm/amd/include/asic_reg/{vega10/VCE => vce}/vce_4_0_default.h (100%) rename drivers/gpu/drm/amd/include/asic_reg/{vega10/VCE => vce}/vce_4_0_offset.h (100%) rename drivers/gpu/drm/amd/include/asic_reg/{vega10/VCE => vce}/vce_4_0_sh_mask.h (100%) delete mode 100644 drivers/gpu/drm/amd/include/asic_reg/vega10/ATHUB/athub_1_0_default.h delete mode 100644 drivers/gpu/drm/amd/include/asic_reg/vega10/ATHUB/athub_1_0_offset.h delete mode 100644 drivers/gpu/drm/amd/include/asic_reg/vega10/ATHUB/athub_1_0_sh_mask.h delete mode 100644 drivers/gpu/drm/amd/include/asic_reg/vega10/DC/dce_12_0_default.h delete mode 100644 drivers/gpu/drm/amd/include/asic_reg/vega10/HDP/hdp_4_0_default.h delete mode 100644 drivers/gpu/drm/amd/include/asic_reg/vega10/HDP/hdp_4_0_offset.h delete mode 100644 drivers/gpu/drm/amd/include/asic_reg/vega10/HDP/hdp_4_0_sh_mask.h delete mode 100644 drivers/gpu/drm/amd/include/asic_reg/vega10/MP/mp_9_0_default.h delete mode 100644 drivers/gpu/drm/amd/include/asic_reg/vega10/MP/mp_9_0_offset.h delete mode 100644 drivers/gpu/drm/amd/include/asic_reg/vega10/MP/mp_9_0_sh_mask.h delete mode 100644 drivers/gpu/drm/amd/include/asic_reg/vega10/NBIF/nbif_6_1_default.h delete mode 100644 drivers/gpu/drm/amd/include/asic_reg/vega10/OSSSYS/osssys_4_0_default.h delete mode 100644 drivers/gpu/drm/amd/include/asic_reg/vega10/SDMA0/sdma0_4_0_default.h delete mode 100644 drivers/gpu/drm/amd/include/asic_reg/vega10/SDMA0/sdma0_4_0_offset.h delete mode 100644 drivers/gpu/drm/amd/include/asic_reg/vega10/SDMA0/sdma0_4_0_sh_mask.h delete mode 100644 drivers/gpu/drm/amd/include/asic_reg/vega10/SDMA1/sdma1_4_0_default.h delete mode 100644 drivers/gpu/drm/amd/include/asic_reg/vega10/SDMA1/sdma1_4_0_offset.h delete mode 100644 drivers/gpu/drm/amd/include/asic_reg/vega10/SDMA1/sdma1_4_0_sh_mask.h delete mode 100644 drivers/gpu/drm/amd/include/asic_reg/vega10/SMUIO/smuio_9_0_default.h delete mode 100644 drivers/gpu/drm/amd/include/asic_reg/vega10/UVD/uvd_7_0_default.h rename drivers/gpu/drm/amd/include/{asic_reg/vega10 => }/soc15ip.h (100%) rename drivers/gpu/drm/amd/include/{asic_reg/vega10 => }/vega10_enum.h (100%) -- 2.7.4
