On Wed, Nov 8, 2017 at 3:41 AM, Rex Zhu <Rex.Zhu at amd.com> wrote:
> Change-Id: I15e562ddff64cf73262ece75f08df60fedc1de1a
> Signed-off-by: Rex Zhu <Rex.Zhu at amd.com>
Acked-by: Alex Deucher <alexander.deucher at amd.com>
> ---
> drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 29 +++++++++++-----------
> drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h | 1 +
> 2 files changed, 16 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> index 7db3fbe..9d4955e 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> @@ -753,6 +753,7 @@ static int vega10_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
> uint32_t config_telemetry = 0;
> struct pp_atomfwctrl_voltage_table vol_table;
> struct cgs_system_info sys_info = {0};
> + uint32_t reg;
>
> data = kzalloc(sizeof(struct vega10_hwmgr), GFP_KERNEL);
> if (data == NULL)
> @@ -859,6 +860,16 @@ static int vega10_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
> advanceFanControlParameters.usFanPWMMinLimit *
> hwmgr->thermal_controller.fanInfo.ulMaxRPM / 100;
>
> + reg = soc15_get_register_offset(DF_HWID, 0,
> + mmDF_CS_AON0_DramBaseAddress0_BASE_IDX,
> + mmDF_CS_AON0_DramBaseAddress0);
> + data->mem_channels = (cgs_read_register(hwmgr->device, reg) &
> + DF_CS_AON0_DramBaseAddress0__IntLvNumChan_MASK) >>
> + DF_CS_AON0_DramBaseAddress0__IntLvNumChan__SHIFT;
> + PP_ASSERT_WITH_CODE(data->mem_channels < ARRAY_SIZE(channel_number),
> + "Mem Channel Index Exceeded maximum!",
> + return -EINVAL);
> +
> return result;
> }
>
> @@ -1777,7 +1788,7 @@ static int vega10_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
> struct vega10_single_dpm_table *dpm_table =
> &(data->dpm_table.mem_table);
> int result = 0;
> - uint32_t i, j, reg, mem_channels;
> + uint32_t i, j;
>
> for (i = 0; i < dpm_table->count; i++) {
> result = vega10_populate_single_memory_level(hwmgr,
> @@ -1801,20 +1812,10 @@ static int vega10_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
> i++;
> }
>
> - reg = soc15_get_register_offset(DF_HWID, 0,
> - mmDF_CS_AON0_DramBaseAddress0_BASE_IDX,
> - mmDF_CS_AON0_DramBaseAddress0);
> - mem_channels = (cgs_read_register(hwmgr->device, reg) &
> - DF_CS_AON0_DramBaseAddress0__IntLvNumChan_MASK) >>
> - DF_CS_AON0_DramBaseAddress0__IntLvNumChan__SHIFT;
> - PP_ASSERT_WITH_CODE(mem_channels < ARRAY_SIZE(channel_number),
> - "Mem Channel Index Exceeded maximum!",
> - return -1);
> -
> - pp_table->NumMemoryChannels = cpu_to_le16(mem_channels);
> + pp_table->NumMemoryChannels = (uint16_t)(data->mem_channels);
> pp_table->MemoryChannelWidth =
> - cpu_to_le16(HBM_MEMORY_CHANNEL_WIDTH *
> - channel_number[mem_channels]);
> + (uint16_t)(HBM_MEMORY_CHANNEL_WIDTH *
> + channel_number[data->mem_channels]);
>
> pp_table->LowestUclkReservedForUlv =
> (uint8_t)(data->lowest_uclk_reserved_for_ulv);
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h
> index b4b461c3..8f7358c 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h
> @@ -389,6 +389,7 @@ struct vega10_hwmgr {
> uint32_t config_telemetry;
> uint32_t smu_version;
> uint32_t acg_loop_state;
> + uint32_t mem_channels;
> };
>
> #define VEGA10_DPM2_NEAR_TDP_DEC 10
> --
> 1.9.1
>
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