Am 07.11.2017 um 08:26 schrieb Pixel Ding:
> From: pding <Pixel.Ding at amd.com>
>
> This lock is used during register accessing in SRIOV guest.
> The register accessing could happen both in irq enabled and
> irq disabled cases. Always use irq-safe lock.
>
> Signed-off-by: pding <Pixel.Ding at amd.com>
Reviewed-by: Christian König <christian.koenig at amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c | 10 ++++++----
> 1 file changed, 6 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
> index 9a73918..733c64c 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
> @@ -120,18 +120,19 @@ void amdgpu_virt_init_setting(struct amdgpu_device *adev)
> uint32_t amdgpu_virt_kiq_rreg(struct amdgpu_device *adev, uint32_t reg)
> {
> signed long r;
> + unsigned long flags;
> uint32_t val, seq;
> struct amdgpu_kiq *kiq = &adev->gfx.kiq;
> struct amdgpu_ring *ring = &kiq->ring;
>
> BUG_ON(!ring->funcs->emit_rreg);
>
> - spin_lock(&kiq->ring_lock);
> + spin_lock_irqsave(&kiq->ring_lock, flags);
> amdgpu_ring_alloc(ring, 32);
> amdgpu_ring_emit_rreg(ring, reg);
> amdgpu_fence_emit_polling(ring, &seq);
> amdgpu_ring_commit(ring);
> - spin_unlock(&kiq->ring_lock);
> + spin_unlock_irqrestore(&kiq->ring_lock, flags);
>
> r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT);
> if (r < 1) {
> @@ -146,18 +147,19 @@ uint32_t amdgpu_virt_kiq_rreg(struct amdgpu_device *adev, uint32_t reg)
> void amdgpu_virt_kiq_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v)
> {
> signed long r;
> + unsigned long flags;
> uint32_t seq;
> struct amdgpu_kiq *kiq = &adev->gfx.kiq;
> struct amdgpu_ring *ring = &kiq->ring;
>
> BUG_ON(!ring->funcs->emit_wreg);
>
> - spin_lock(&kiq->ring_lock);
> + spin_lock_irqsave(&kiq->ring_lock, flags);
> amdgpu_ring_alloc(ring, 32);
> amdgpu_ring_emit_wreg(ring, reg, v);
> amdgpu_fence_emit_polling(ring, &seq);
> amdgpu_ring_commit(ring);
> - spin_unlock(&kiq->ring_lock);
> + spin_unlock_irqrestore(&kiq->ring_lock, flags);
>
> r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT);
> if (r < 1)
