[PATCH 2/2] drm/amdgpu: use irq-safe lock for adev->ring_lru_list_lock

[Pixel.Ding@xxxxxxx (Pixel Ding)]

From: pding <Pixel.Ding@xxxxxxx>

This lock is used during register accessing in SRIOV guest
since KIQ uses general ring submission (amdgpu_ring_commit).
The register accessing could happen both in irq enabled and
irq disabled cases. Always use irq-safe lock.

Signed-off-by: pding <Pixel.Ding at amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c | 11 +++++++----
 1 file changed, 7 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
index e5ece1f..d7997b5 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
@@ -401,11 +401,12 @@ int amdgpu_ring_lru_get(struct amdgpu_device *adev, int type,
 			bool lru_pipe_order, struct amdgpu_ring **ring)
 {
 	struct amdgpu_ring *entry;
+	unsigned long flags;
 
 	/* List is sorted in LRU order, find first entry corresponding
 	 * to the desired HW IP */
 	*ring = NULL;
-	spin_lock(&adev->ring_lru_list_lock);
+	spin_lock_irqsave(&adev->ring_lru_list_lock, flags);
 	list_for_each_entry(entry, &adev->ring_lru_list, lru_list) {
 		if (entry->funcs->type != type)
 			continue;
@@ -430,7 +431,7 @@ int amdgpu_ring_lru_get(struct amdgpu_device *adev, int type,
 	if (*ring)
 		amdgpu_ring_lru_touch_locked(adev, *ring);
 
-	spin_unlock(&adev->ring_lru_list_lock);
+	spin_unlock_irqrestore(&adev->ring_lru_list_lock, flags);
 
 	if (!*ring) {
 		DRM_ERROR("Ring LRU contains no entries for ring type:%d\n", type);
@@ -450,9 +451,11 @@ int amdgpu_ring_lru_get(struct amdgpu_device *adev, int type,
  */
 void amdgpu_ring_lru_touch(struct amdgpu_device *adev, struct amdgpu_ring *ring)
 {
-	spin_lock(&adev->ring_lru_list_lock);
+	unsigned long flags;
+
+	spin_lock_irqsave(&adev->ring_lru_list_lock, flags);
 	amdgpu_ring_lru_touch_locked(adev, ring);
-	spin_unlock(&adev->ring_lru_list_lock);
+	spin_unlock_irqrestore(&adev->ring_lru_list_lock, flags);
 }
 
 /*
-- 
2.9.5