Signed-off-by: Huang Rui <ray.huang at amd.com>
---
drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c | 55 ++++++++++++++++---------------
drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c | 56 +++++++++++++++++---------------
2 files changed, 59 insertions(+), 52 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
index 5fdc9be..7b3447a 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
@@ -187,33 +187,10 @@ static void gfxhub_v1_0_dis_identity_aperture(struct amdgpu_device *adev)
}
-int gfxhub_v1_0_gart_enable(struct amdgpu_device *adev)
+static void gfxhub_v1_0_setup_vmid_config(struct amdgpu_device *adev)
{
- u32 tmp;
- u32 i;
-
- DRM_INFO("%s -- in\n", __func__);
- if (amdgpu_sriov_vf(adev)) {
- /*
- * MC_VM_FB_LOCATION_BASE/TOP is NULL for VF, becuase they are
- * VF copy registers so vbios post doesn't program them, for
- * SRIOV driver need to program them
- */
- WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_FB_LOCATION_BASE),
- adev->mc.vram_start >> 24);
- WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_FB_LOCATION_TOP),
- adev->mc.vram_end >> 24);
- }
-
- /* GART Enable. */
- gfxhub_v1_0_init_pt_regs(adev);
- gfxhub_v1_0_init_gart_aperture_regs(adev);
- gfxhub_v1_0_init_system_aperture_regs(adev);
- gfxhub_v1_0_init_tlb_regs(adev);
- gfxhub_v1_0_init_cache_regs(adev);
-
- gfxhub_v1_0_enable_system_domain(adev);
- gfxhub_v1_0_dis_identity_aperture(adev);
+ int i;
+ uint32_t tmp;
for (i = 0; i <= 14; i++) {
tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT1_CNTL) + i);
@@ -248,7 +225,33 @@ int gfxhub_v1_0_gart_enable(struct amdgpu_device *adev)
WREG32(SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32) + i*2,
upper_32_bits(adev->vm_manager.max_pfn - 1));
}
+}
+
+int gfxhub_v1_0_gart_enable(struct amdgpu_device *adev)
+{
+ DRM_INFO("%s -- in\n", __func__);
+ if (amdgpu_sriov_vf(adev)) {
+ /*
+ * MC_VM_FB_LOCATION_BASE/TOP is NULL for VF, becuase they are
+ * VF copy registers so vbios post doesn't program them, for
+ * SRIOV driver need to program them
+ */
+ WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_FB_LOCATION_BASE),
+ adev->mc.vram_start >> 24);
+ WREG32(SOC15_REG_OFFSET(GC, 0, mmMC_VM_FB_LOCATION_TOP),
+ adev->mc.vram_end >> 24);
+ }
+ /* GART Enable. */
+ gfxhub_v1_0_init_pt_regs(adev);
+ gfxhub_v1_0_init_gart_aperture_regs(adev);
+ gfxhub_v1_0_init_system_aperture_regs(adev);
+ gfxhub_v1_0_init_tlb_regs(adev);
+ gfxhub_v1_0_init_cache_regs(adev);
+
+ gfxhub_v1_0_enable_system_domain(adev);
+ gfxhub_v1_0_dis_identity_aperture(adev);
+ gfxhub_v1_0_setup_vmid_config(adev);
return 0;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
index 84148578..536aa86 100644
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
@@ -199,33 +199,10 @@ static void mmhub_v1_0_dis_identity_aperture(struct amdgpu_device *adev)
mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32), 0);
}
-int mmhub_v1_0_gart_enable(struct amdgpu_device *adev)
+static void mmhub_v1_0_setup_vmid_config(struct amdgpu_device *adev)
{
- u32 tmp;
- u32 i;
-
- DRM_INFO("%s -- in\n", __func__);
- if (amdgpu_sriov_vf(adev)) {
- /*
- * MC_VM_FB_LOCATION_BASE/TOP is NULL for VF, becuase they are
- * VF copy registers so vbios post doesn't program them, for
- * SRIOV driver need to program them
- */
- WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmMC_VM_FB_LOCATION_BASE),
- adev->mc.vram_start >> 24);
- WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmMC_VM_FB_LOCATION_TOP),
- adev->mc.vram_end >> 24);
- }
-
- /* GART Enable. */
- mmhub_v1_0_init_pt_regs(adev);
- mmhub_v1_0_init_gart_aperture_regs(adev);
- mmhub_v1_0_init_system_aperture_regs(adev);
- mmhub_v1_0_init_tlb_regs(adev);
- mmhub_v1_0_init_cache_regs(adev);
-
- mmhub_v1_0_enable_system_domain(adev);
- mmhub_v1_0_dis_identity_aperture(adev);
+ int i;
+ uint32_t tmp;
for (i = 0; i <= 14; i++) {
tmp = RREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_CONTEXT1_CNTL)
@@ -262,6 +239,33 @@ int mmhub_v1_0_gart_enable(struct amdgpu_device *adev)
WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32) + i*2,
upper_32_bits(adev->vm_manager.max_pfn - 1));
}
+}
+
+int mmhub_v1_0_gart_enable(struct amdgpu_device *adev)
+{
+ DRM_INFO("%s -- in\n", __func__);
+ if (amdgpu_sriov_vf(adev)) {
+ /*
+ * MC_VM_FB_LOCATION_BASE/TOP is NULL for VF, becuase they are
+ * VF copy registers so vbios post doesn't program them, for
+ * SRIOV driver need to program them
+ */
+ WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmMC_VM_FB_LOCATION_BASE),
+ adev->mc.vram_start >> 24);
+ WREG32(SOC15_REG_OFFSET(MMHUB, 0, mmMC_VM_FB_LOCATION_TOP),
+ adev->mc.vram_end >> 24);
+ }
+
+ /* GART Enable. */
+ mmhub_v1_0_init_pt_regs(adev);
+ mmhub_v1_0_init_gart_aperture_regs(adev);
+ mmhub_v1_0_init_system_aperture_regs(adev);
+ mmhub_v1_0_init_tlb_regs(adev);
+ mmhub_v1_0_init_cache_regs(adev);
+
+ mmhub_v1_0_enable_system_domain(adev);
+ mmhub_v1_0_dis_identity_aperture(adev);
+ mmhub_v1_0_setup_vmid_config(adev);
return 0;
}
--
2.7.4
