Replace uNN with uintNN_t types. In various places
uintNN_t was already used.
Signed-off-by: Tom St Denis <tom.stdenis at amd.com>
---
drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 204 +++++++++++++++++-----------------
1 file changed, 102 insertions(+), 102 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
index af6c5b8d0a40..1b6b9b22d780 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
@@ -47,7 +47,7 @@
static void dce_v6_0_set_display_funcs(struct amdgpu_device *adev);
static void dce_v6_0_set_irq_funcs(struct amdgpu_device *adev);
-static const u32 crtc_offsets[6] =
+static const uint32_t crtc_offsets[6] =
{
SI_CRTC0_REGISTER_OFFSET,
SI_CRTC1_REGISTER_OFFSET,
@@ -57,7 +57,7 @@ static const u32 crtc_offsets[6] =
SI_CRTC5_REGISTER_OFFSET
};
-static const u32 hpd_offsets[] =
+static const uint32_t hpd_offsets[] =
{
mmDC_HPD1_INT_STATUS - mmDC_HPD1_INT_STATUS,
mmDC_HPD2_INT_STATUS - mmDC_HPD1_INT_STATUS,
@@ -115,11 +115,11 @@ static const struct {
.hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK
} };
-static u32 dce_v6_0_audio_endpt_rreg(struct amdgpu_device *adev,
- u32 block_offset, u32 reg)
+static uint32_t dce_v6_0_audio_endpt_rreg(struct amdgpu_device *adev,
+ uint32_t block_offset, uint32_t reg)
{
unsigned long flags;
- u32 r;
+ uint32_t r;
spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
@@ -130,7 +130,7 @@ static u32 dce_v6_0_audio_endpt_rreg(struct amdgpu_device *adev,
}
static void dce_v6_0_audio_endpt_wreg(struct amdgpu_device *adev,
- u32 block_offset, u32 reg, u32 v)
+ uint32_t block_offset, uint32_t reg, uint32_t v)
{
unsigned long flags;
@@ -151,7 +151,7 @@ static bool dce_v6_0_is_in_vblank(struct amdgpu_device *adev, int crtc)
static bool dce_v6_0_is_counter_moving(struct amdgpu_device *adev, int crtc)
{
- u32 pos1, pos2;
+ uint32_t pos1, pos2;
pos1 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
pos2 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
@@ -199,7 +199,7 @@ static void dce_v6_0_vblank_wait(struct amdgpu_device *adev, int crtc)
}
}
-static u32 dce_v6_0_vblank_get_counter(struct amdgpu_device *adev, int crtc)
+static uint32_t dce_v6_0_vblank_get_counter(struct amdgpu_device *adev, int crtc)
{
if (crtc >= adev->mode_info.num_crtc)
return 0;
@@ -239,7 +239,7 @@ static void dce_v6_0_pageflip_interrupt_fini(struct amdgpu_device *adev)
* Returns the current update pending status.
*/
static void dce_v6_0_page_flip(struct amdgpu_device *adev,
- int crtc_id, u64 crtc_base, bool async)
+ int crtc_id, uint64_t crtc_base, bool async)
{
struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
@@ -250,14 +250,14 @@ static void dce_v6_0_page_flip(struct amdgpu_device *adev,
WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
upper_32_bits(crtc_base));
WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
- (u32)crtc_base);
+ (uint32_t)crtc_base);
/* post the write */
RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset);
}
static int dce_v6_0_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
- u32 *vbl, u32 *position)
+ uint32_t *vbl, uint32_t *position)
{
if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
return -EINVAL;
@@ -302,7 +302,7 @@ static bool dce_v6_0_hpd_sense(struct amdgpu_device *adev,
static void dce_v6_0_hpd_set_polarity(struct amdgpu_device *adev,
enum amdgpu_hpd_id hpd)
{
- u32 tmp;
+ uint32_t tmp;
bool connected = dce_v6_0_hpd_sense(adev, hpd);
if (hpd >= adev->mode_info.num_hpd)
@@ -328,7 +328,7 @@ static void dce_v6_0_hpd_init(struct amdgpu_device *adev)
{
struct drm_device *dev = adev->ddev;
struct drm_connector *connector;
- u32 tmp;
+ uint32_t tmp;
list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
@@ -371,7 +371,7 @@ static void dce_v6_0_hpd_fini(struct amdgpu_device *adev)
{
struct drm_device *dev = adev->ddev;
struct drm_connector *connector;
- u32 tmp;
+ uint32_t tmp;
list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
@@ -387,12 +387,12 @@ static void dce_v6_0_hpd_fini(struct amdgpu_device *adev)
}
}
-static u32 dce_v6_0_hpd_get_gpio_reg(struct amdgpu_device *adev)
+static uint32_t dce_v6_0_hpd_get_gpio_reg(struct amdgpu_device *adev)
{
return mmDC_GPIO_HPD_A;
}
-static u32 evergreen_get_vblank_counter(struct amdgpu_device* adev, int crtc)
+static uint32_t evergreen_get_vblank_counter(struct amdgpu_device* adev, int crtc)
{
if (crtc >= adev->mode_info.num_crtc)
return 0;
@@ -403,7 +403,7 @@ static u32 evergreen_get_vblank_counter(struct amdgpu_device* adev, int crtc)
static void dce_v6_0_stop_mc_access(struct amdgpu_device *adev,
struct amdgpu_mode_mc_save *save)
{
- u32 crtc_enabled, tmp, frame_count;
+ uint32_t crtc_enabled, tmp, frame_count;
int i, j;
save->vga_render_control = RREG32(mmVGA_RENDER_CONTROL);
@@ -451,7 +451,7 @@ static void dce_v6_0_stop_mc_access(struct amdgpu_device *adev,
static void dce_v6_0_resume_mc_access(struct amdgpu_device *adev,
struct amdgpu_mode_mc_save *save)
{
- u32 tmp;
+ uint32_t tmp;
int i, j;
/* update crtc base addresses */
@@ -461,13 +461,13 @@ static void dce_v6_0_resume_mc_access(struct amdgpu_device *adev,
WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i],
upper_32_bits(adev->mc.vram_start));
WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i],
- (u32)adev->mc.vram_start);
+ (uint32_t)adev->mc.vram_start);
WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + crtc_offsets[i],
- (u32)adev->mc.vram_start);
+ (uint32_t)adev->mc.vram_start);
}
WREG32(mmVGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(adev->mc.vram_start));
- WREG32(mmVGA_MEMORY_BASE_ADDRESS, (u32)adev->mc.vram_start);
+ WREG32(mmVGA_MEMORY_BASE_ADDRESS, (uint32_t)adev->mc.vram_start);
/* unlock regs and wait for update */
for (i = 0; i < adev->mode_info.num_crtc; i++) {
@@ -535,7 +535,7 @@ void dce_v6_0_disable_dce(struct amdgpu_device *adev)
{
/*Disable VGA render and enabled crtc, if has DCE engine*/
if (amdgpu_atombios_has_dce_engine_info(adev)) {
- u32 tmp;
+ uint32_t tmp;
int crtc_enabled, i;
dce_v6_0_set_vga_render_state(adev, false);
@@ -564,7 +564,7 @@ static void dce_v6_0_program_fmt(struct drm_encoder *encoder)
struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
int bpc = 0;
- u32 tmp = 0;
+ uint32_t tmp = 0;
enum amdgpu_connector_dither dither = AMDGPU_FMT_DITHER_DISABLE;
if (connector) {
@@ -621,9 +621,9 @@ static void dce_v6_0_program_fmt(struct drm_encoder *encoder)
* Used for display watermark bandwidth calculations
* Returns the number of dram channels
*/
-static u32 si_get_number_of_dram_channels(struct amdgpu_device *adev)
+static uint32_t si_get_number_of_dram_channels(struct amdgpu_device *adev)
{
- u32 tmp = RREG32(mmMC_SHARED_CHMAP);
+ uint32_t tmp = RREG32(mmMC_SHARED_CHMAP);
switch ((tmp & MC_SHARED_CHMAP__NOOFCHAN_MASK) >> MC_SHARED_CHMAP__NOOFCHAN__SHIFT) {
case 0:
@@ -649,19 +649,19 @@ static u32 si_get_number_of_dram_channels(struct amdgpu_device *adev)
}
struct dce6_wm_params {
- u32 dram_channels; /* number of dram channels */
- u32 yclk; /* bandwidth per dram data pin in kHz */
- u32 sclk; /* engine clock in kHz */
- u32 disp_clk; /* display clock in kHz */
- u32 src_width; /* viewport width */
- u32 active_time; /* active display time in ns */
- u32 blank_time; /* blank time in ns */
+ uint32_t dram_channels; /* number of dram channels */
+ uint32_t yclk; /* bandwidth per dram data pin in kHz */
+ uint32_t sclk; /* engine clock in kHz */
+ uint32_t disp_clk; /* display clock in kHz */
+ uint32_t src_width; /* viewport width */
+ uint32_t active_time; /* active display time in ns */
+ uint32_t blank_time; /* blank time in ns */
bool interlaced; /* mode is interlaced */
fixed20_12 vsc; /* vertical scale ratio */
- u32 num_heads; /* number of active crtcs */
- u32 bytes_per_pixel; /* bytes per pixel display + overlay */
- u32 lb_size; /* line buffer allocated to pipe */
- u32 vtaps; /* vertical scaler taps */
+ uint32_t num_heads; /* number of active crtcs */
+ uint32_t bytes_per_pixel; /* bytes per pixel display + overlay */
+ uint32_t lb_size; /* line buffer allocated to pipe */
+ uint32_t vtaps; /* vertical scaler taps */
};
/**
@@ -673,7 +673,7 @@ struct dce6_wm_params {
* Used for display watermark bandwidth calculations
* Returns the dram bandwidth in MBytes/s
*/
-static u32 dce_v6_0_dram_bandwidth(struct dce6_wm_params *wm)
+static uint32_t dce_v6_0_dram_bandwidth(struct dce6_wm_params *wm)
{
/* Calculate raw DRAM Bandwidth */
fixed20_12 dram_efficiency; /* 0.7 */
@@ -702,7 +702,7 @@ static u32 dce_v6_0_dram_bandwidth(struct dce6_wm_params *wm)
* Used for display watermark bandwidth calculations
* Returns the dram bandwidth for display in MBytes/s
*/
-static u32 dce_v6_0_dram_bandwidth_for_display(struct dce6_wm_params *wm)
+static uint32_t dce_v6_0_dram_bandwidth_for_display(struct dce6_wm_params *wm)
{
/* Calculate DRAM Bandwidth and the part allocated to display. */
fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
@@ -731,7 +731,7 @@ static u32 dce_v6_0_dram_bandwidth_for_display(struct dce6_wm_params *wm)
* Used for display watermark bandwidth calculations
* Returns the data return bandwidth in MBytes/s
*/
-static u32 dce_v6_0_data_return_bandwidth(struct dce6_wm_params *wm)
+static uint32_t dce_v6_0_data_return_bandwidth(struct dce6_wm_params *wm)
{
/* Calculate the display Data return Bandwidth */
fixed20_12 return_efficiency; /* 0.8 */
@@ -760,7 +760,7 @@ static u32 dce_v6_0_data_return_bandwidth(struct dce6_wm_params *wm)
* Used for display watermark bandwidth calculations
* Returns the dmif bandwidth in MBytes/s
*/
-static u32 dce_v6_0_dmif_request_bandwidth(struct dce6_wm_params *wm)
+static uint32_t dce_v6_0_dmif_request_bandwidth(struct dce6_wm_params *wm)
{
/* Calculate the DMIF Request Bandwidth */
fixed20_12 disp_clk_request_efficiency; /* 0.8 */
@@ -791,12 +791,12 @@ static u32 dce_v6_0_dmif_request_bandwidth(struct dce6_wm_params *wm)
* Used for display watermark bandwidth calculations
* Returns the min available bandwidth in MBytes/s
*/
-static u32 dce_v6_0_available_bandwidth(struct dce6_wm_params *wm)
+static uint32_t dce_v6_0_available_bandwidth(struct dce6_wm_params *wm)
{
/* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
- u32 dram_bandwidth = dce_v6_0_dram_bandwidth(wm);
- u32 data_return_bandwidth = dce_v6_0_data_return_bandwidth(wm);
- u32 dmif_req_bandwidth = dce_v6_0_dmif_request_bandwidth(wm);
+ uint32_t dram_bandwidth = dce_v6_0_dram_bandwidth(wm);
+ uint32_t data_return_bandwidth = dce_v6_0_data_return_bandwidth(wm);
+ uint32_t dmif_req_bandwidth = dce_v6_0_dmif_request_bandwidth(wm);
return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));
}
@@ -810,7 +810,7 @@ static u32 dce_v6_0_available_bandwidth(struct dce6_wm_params *wm)
* Used for display watermark bandwidth calculations
* Returns the average available bandwidth in MBytes/s
*/
-static u32 dce_v6_0_average_bandwidth(struct dce6_wm_params *wm)
+static uint32_t dce_v6_0_average_bandwidth(struct dce6_wm_params *wm)
{
/* Calculate the display mode Average Bandwidth
* DisplayMode should contain the source and destination dimensions,
@@ -843,19 +843,19 @@ static u32 dce_v6_0_average_bandwidth(struct dce6_wm_params *wm)
* Used for display watermark bandwidth calculations
* Returns the latency watermark in ns
*/
-static u32 dce_v6_0_latency_watermark(struct dce6_wm_params *wm)
+static uint32_t dce_v6_0_latency_watermark(struct dce6_wm_params *wm)
{
/* First calculate the latency in ns */
- u32 mc_latency = 2000; /* 2000 ns. */
- u32 available_bandwidth = dce_v6_0_available_bandwidth(wm);
- u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
- u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
- u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
- u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
+ uint32_t mc_latency = 2000; /* 2000 ns. */
+ uint32_t available_bandwidth = dce_v6_0_available_bandwidth(wm);
+ uint32_t worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
+ uint32_t cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
+ uint32_t dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
+ uint32_t other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
(wm->num_heads * cursor_line_pair_return_time);
- u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
- u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
- u32 tmp, dmif_size = 12288;
+ uint32_t latency = mc_latency + other_heads_data_return_time + dc_latency;
+ uint32_t max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
+ uint32_t tmp, dmif_size = 12288;
fixed20_12 a, b, c;
if (wm->num_heads == 0)
@@ -874,7 +874,7 @@ static u32 dce_v6_0_latency_watermark(struct dce6_wm_params *wm)
a.full = dfixed_const(available_bandwidth);
b.full = dfixed_const(wm->num_heads);
a.full = dfixed_div(a, b);
- tmp = div_u64((u64) dmif_size * (u64) wm->disp_clk, mc_latency + 512);
+ tmp = div_u64((uint64_t) dmif_size * (uint64_t) wm->disp_clk, mc_latency + 512);
tmp = min(dfixed_trunc(a), tmp);
lb_fill_bw = min(tmp, wm->disp_clk * wm->bytes_per_pixel / 1000);
@@ -944,10 +944,10 @@ static bool dce_v6_0_average_bandwidth_vs_available_bandwidth(struct dce6_wm_par
*/
static bool dce_v6_0_check_latency_hiding(struct dce6_wm_params *wm)
{
- u32 lb_partitions = wm->lb_size / wm->src_width;
- u32 line_time = wm->active_time + wm->blank_time;
- u32 latency_tolerant_lines;
- u32 latency_hiding;
+ uint32_t lb_partitions = wm->lb_size / wm->src_width;
+ uint32_t line_time = wm->active_time + wm->blank_time;
+ uint32_t latency_tolerant_lines;
+ uint32_t latency_hiding;
fixed20_12 a;
a.full = dfixed_const(1);
@@ -981,23 +981,23 @@ static bool dce_v6_0_check_latency_hiding(struct dce6_wm_params *wm)
*/
static void dce_v6_0_program_watermarks(struct amdgpu_device *adev,
struct amdgpu_crtc *amdgpu_crtc,
- u32 lb_size, u32 num_heads)
+ uint32_t lb_size, uint32_t num_heads)
{
struct drm_display_mode *mode = &amdgpu_crtc->base.mode;
struct dce6_wm_params wm_low, wm_high;
- u32 dram_channels;
- u32 active_time;
- u32 line_time = 0;
- u32 latency_watermark_a = 0, latency_watermark_b = 0;
- u32 priority_a_mark = 0, priority_b_mark = 0;
- u32 priority_a_cnt = PRIORITY_OFF;
- u32 priority_b_cnt = PRIORITY_OFF;
- u32 tmp, arb_control3, lb_vblank_lead_lines = 0;
+ uint32_t dram_channels;
+ uint32_t active_time;
+ uint32_t line_time = 0;
+ uint32_t latency_watermark_a = 0, latency_watermark_b = 0;
+ uint32_t priority_a_mark = 0, priority_b_mark = 0;
+ uint32_t priority_a_cnt = PRIORITY_OFF;
+ uint32_t priority_b_cnt = PRIORITY_OFF;
+ uint32_t tmp, arb_control3, lb_vblank_lead_lines = 0;
fixed20_12 a, b, c;
if (amdgpu_crtc->base.enabled && num_heads && mode) {
- active_time = 1000000UL * (u32)mode->crtc_hdisplay / (u32)mode->clock;
- line_time = min((u32) (1000000UL * (u32)mode->crtc_htotal / (u32)mode->clock), (u32)65535);
+ active_time = 1000000UL * (uint32_t)mode->crtc_hdisplay / (uint32_t)mode->clock;
+ line_time = min((uint32_t) (1000000UL * (uint32_t)mode->crtc_htotal / (uint32_t)mode->clock), (uint32_t)65535);
priority_a_cnt = 0;
priority_b_cnt = 0;
@@ -1058,9 +1058,9 @@ static void dce_v6_0_program_watermarks(struct amdgpu_device *adev,
wm_low.num_heads = num_heads;
/* set for high clocks */
- latency_watermark_a = min(dce_v6_0_latency_watermark(&wm_high), (u32)65535);
+ latency_watermark_a = min(dce_v6_0_latency_watermark(&wm_high), (uint32_t)65535);
/* set for low clocks */
- latency_watermark_b = min(dce_v6_0_latency_watermark(&wm_low), (u32)65535);
+ latency_watermark_b = min(dce_v6_0_latency_watermark(&wm_low), (uint32_t)65535);
/* possibly force display priority to high */
/* should really do this at mode validation time... */
@@ -1141,13 +1141,13 @@ static void dce_v6_0_program_watermarks(struct amdgpu_device *adev,
}
/* watermark setup */
-static u32 dce_v6_0_line_buffer_adjust(struct amdgpu_device *adev,
+static uint32_t dce_v6_0_line_buffer_adjust(struct amdgpu_device *adev,
struct amdgpu_crtc *amdgpu_crtc,
struct drm_display_mode *mode,
struct drm_display_mode *other_mode)
{
- u32 tmp, buffer_alloc, i;
- u32 pipe_offset = amdgpu_crtc->crtc_id * 0x8;
+ uint32_t tmp, buffer_alloc, i;
+ uint32_t pipe_offset = amdgpu_crtc->crtc_id * 0x8;
/*
* Line Buffer Setup
* There are 3 line buffers, each one shared by 2 display controllers.
@@ -1214,7 +1214,7 @@ static void dce_v6_0_bandwidth_update(struct amdgpu_device *adev)
{
struct drm_display_mode *mode0 = NULL;
struct drm_display_mode *mode1 = NULL;
- u32 num_heads = 0, lb_size;
+ uint32_t num_heads = 0, lb_size;
int i;
if (!adev->mode_info.mode_config_initialized)
@@ -1239,7 +1239,7 @@ static void dce_v6_0_bandwidth_update(struct amdgpu_device *adev)
static void dce_v6_0_audio_get_connected_pins(struct amdgpu_device *adev)
{
int i;
- u32 tmp;
+ uint32_t tmp;
for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
tmp = RREG32_AUDIO_ENDPT(adev->mode_info.audio.pin[i].offset,
@@ -1290,7 +1290,7 @@ static void dce_v6_0_audio_write_latency_fields(struct drm_encoder *encoder,
struct drm_connector *connector;
struct amdgpu_connector *amdgpu_connector = NULL;
int interlace = 0;
- u32 tmp;
+ uint32_t tmp;
list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
if (connector->encoder == encoder) {
@@ -1331,7 +1331,7 @@ static void dce_v6_0_audio_write_speaker_allocation(struct drm_encoder *encoder)
struct amdgpu_connector *amdgpu_connector = NULL;
u8 *sadb = NULL;
int sad_count;
- u32 tmp;
+ uint32_t tmp;
list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
if (connector->encoder == encoder) {
@@ -1423,7 +1423,7 @@ static void dce_v6_0_audio_write_sad_regs(struct drm_encoder *encoder)
}
for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {
- u32 tmp = 0;
+ uint32_t tmp = 0;
u8 stereo_freqs = 0;
int max_channels = -1;
int j;
@@ -1469,7 +1469,7 @@ static void dce_v6_0_audio_enable(struct amdgpu_device *adev,
enable ? AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK : 0);
}
-static const u32 pin_offsets[7] =
+static const uint32_t pin_offsets[7] =
{
(0x1780 - 0x1780),
(0x1786 - 0x1780),
@@ -1538,7 +1538,7 @@ static void dce_v6_0_audio_set_vbi_packet(struct drm_encoder *encoder)
struct amdgpu_device *adev = dev->dev_private;
struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
- u32 tmp;
+ uint32_t tmp;
tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset);
tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1);
@@ -1555,7 +1555,7 @@ static void dce_v6_0_audio_set_acr(struct drm_encoder *encoder,
struct amdgpu_afmt_acr acr = amdgpu_afmt_acr(clock);
struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
- u32 tmp;
+ uint32_t tmp;
tmp = RREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset);
tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, 1);
@@ -1597,7 +1597,7 @@ static void dce_v6_0_audio_set_avi_infoframe(struct drm_encoder *encoder,
uint8_t *payload = buffer + 3;
uint8_t *header = buffer;
ssize_t err;
- u32 tmp;
+ uint32_t tmp;
err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode);
if (err < 0) {
@@ -1627,13 +1627,13 @@ static void dce_v6_0_audio_set_avi_infoframe(struct drm_encoder *encoder,
WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp);
}
-static void dce_v6_0_audio_set_dto(struct drm_encoder *encoder, u32 clock)
+static void dce_v6_0_audio_set_dto(struct drm_encoder *encoder, uint32_t clock)
{
struct drm_device *dev = encoder->dev;
struct amdgpu_device *adev = dev->dev_private;
struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
int em = amdgpu_atombios_encoder_get_encoder_mode(encoder);
- u32 tmp;
+ uint32_t tmp;
/*
* Two dtos: generally use dto0 for hdmi, dto1 for dp.
@@ -1667,7 +1667,7 @@ static void dce_v6_0_audio_set_packet(struct drm_encoder *encoder)
struct amdgpu_device *adev = dev->dev_private;
struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
- u32 tmp;
+ uint32_t tmp;
tmp = RREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset);
tmp = REG_SET_FIELD(tmp, AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1);
@@ -1711,7 +1711,7 @@ static void dce_v6_0_audio_set_mute(struct drm_encoder *encoder, bool mute)
struct amdgpu_device *adev = dev->dev_private;
struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
- u32 tmp;
+ uint32_t tmp;
tmp = RREG32(mmHDMI_GC + dig->afmt->offset);
tmp = REG_SET_FIELD(tmp, HDMI_GC, HDMI_GC_AVMUTE, mute ? 1 : 0);
@@ -1724,7 +1724,7 @@ static void dce_v6_0_audio_hdmi_enable(struct drm_encoder *encoder, bool enable)
struct amdgpu_device *adev = dev->dev_private;
struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
- u32 tmp;
+ uint32_t tmp;
if (enable) {
tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset);
@@ -1761,7 +1761,7 @@ static void dce_v6_0_audio_dp_enable(struct drm_encoder *encoder, bool enable)
struct amdgpu_device *adev = dev->dev_private;
struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
- u32 tmp;
+ uint32_t tmp;
if (enable) {
tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);
@@ -1913,7 +1913,7 @@ static void dce_v6_0_afmt_fini(struct amdgpu_device *adev)
}
}
-static const u32 vga_control_regs[6] =
+static const uint32_t vga_control_regs[6] =
{
mmD1VGA_CONTROL,
mmD2VGA_CONTROL,
@@ -1928,7 +1928,7 @@ static void dce_v6_0_vga_enable(struct drm_crtc *crtc, bool enable)
struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
struct drm_device *dev = crtc->dev;
struct amdgpu_device *adev = dev->dev_private;
- u32 vga_control;
+ uint32_t vga_control;
vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1;
WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | (enable ? 1 : 0));
@@ -1956,8 +1956,8 @@ static int dce_v6_0_crtc_do_set_base(struct drm_crtc *crtc,
struct amdgpu_bo *abo;
uint64_t fb_location, tiling_flags;
uint32_t fb_format, fb_pitch_pixels, pipe_config;
- u32 fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_NONE);
- u32 viewport_w, viewport_h;
+ uint32_t fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_NONE);
+ uint32_t viewport_w, viewport_h;
int r;
bool bypass_lut = false;
struct drm_format_name_buf format_name;
@@ -2102,9 +2102,9 @@ static int dce_v6_0_crtc_do_set_base(struct drm_crtc *crtc,
WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
upper_32_bits(fb_location));
WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
- (u32)fb_location & GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK);
+ (uint32_t)fb_location & GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK);
WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
- (u32) fb_location & GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK);
+ (uint32_t) fb_location & GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK);
WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format);
WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap);
@@ -2275,12 +2275,12 @@ static int dce_v6_0_pick_dig_encoder(struct drm_encoder *encoder)
*
*
*/
-static u32 dce_v6_0_pick_pll(struct drm_crtc *crtc)
+static uint32_t dce_v6_0_pick_pll(struct drm_crtc *crtc)
{
struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
struct drm_device *dev = crtc->dev;
struct amdgpu_device *adev = dev->dev_private;
- u32 pll_in_use;
+ uint32_t pll_in_use;
int pll;
if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) {
@@ -2949,7 +2949,7 @@ static void dce_v6_0_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev,
int crtc,
enum amdgpu_interrupt_state state)
{
- u32 reg_block, interrupt_mask;
+ uint32_t reg_block, interrupt_mask;
if (crtc >= adev->mode_info.num_crtc) {
DRM_DEBUG("invalid crtc %d\n", crtc);
@@ -3008,7 +3008,7 @@ static int dce_v6_0_set_hpd_interrupt_state(struct amdgpu_device *adev,
unsigned type,
enum amdgpu_interrupt_state state)
{
- u32 dc_hpd_int_cntl;
+ uint32_t dc_hpd_int_cntl;
if (type >= adev->mode_info.num_hpd) {
DRM_DEBUG("invalid hdp %d\n", type);
@@ -3122,7 +3122,7 @@ static int dce_v6_0_set_pageflip_interrupt_state(struct amdgpu_device *adev,
unsigned type,
enum amdgpu_interrupt_state state)
{
- u32 reg;
+ uint32_t reg;
if (type >= adev->mode_info.num_crtc) {
DRM_ERROR("invalid pageflip crtc %d\n", type);
--
2.12.0
