[Public]
> -----Original Message-----
> From: amd-gfx <amd-gfx-bounces@xxxxxxxxxxxxxxxxxxxxx> On Behalf Of Alex
> Deucher
> Sent: Thursday, March 13, 2025 2:57 AM
> To: amd-gfx@xxxxxxxxxxxxxxxxxxxxx
> Cc: Deucher, Alexander <Alexander.Deucher@xxxxxxx>; Khatri, Sunil
> <Sunil.Khatri@xxxxxxx>
> Subject: [PATCH 05/11] drm/amdgpu/mes: update hqd masks when disable_kq is
> set
>
> Make all resources available to user queues.
>
> Suggested-by: Sunil Khatri <sunil.khatri@xxxxxxx>
> Reviewed-by: Sunil Khatri <sunil.khatri@xxxxxxx>
> Signed-off-by: Alex Deucher <alexander.deucher@xxxxxxx>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
> index 5abc1ca0fee98..971bf01fe46a9 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
> @@ -120,21 +120,21 @@ int amdgpu_mes_init(struct amdgpu_device *adev)
> * Set GFX pipe 0 queue 1-7 for MES scheduling
> * mask = 1111 1110b
> */
> - adev->mes.gfx_hqd_mask[i] = 0xFE;
> + adev->mes.gfx_hqd_mask[i] = adev->gfx.disable_kq ?
> 0xFF : 0xFE;
> else
> /*
> * GFX pipe 0 queue 0 is being used by Kernel queue.
> * Set GFX pipe 0 queue 1 for MES scheduling
> * mask = 10b
> */
> - adev->mes.gfx_hqd_mask[i] = 0x2;
> + adev->mes.gfx_hqd_mask[i] = adev->gfx.disable_kq ? 0x3 :
> 0x2;
> }
>
> for (i = 0; i < AMDGPU_MES_MAX_COMPUTE_PIPES; i++) {
> /* use only 1st MEC pipes */
> if (i >= adev->gfx.mec.num_pipe_per_mec)
> continue;
> - adev->mes.compute_hqd_mask[i] = 0xc;
> + adev->mes.compute_hqd_mask[i] = adev->gfx.disable_kq ? 0xF :
> 0xC;
> }
Question: Why there are still only partial gfx(queue[0,1]) and compute(queue[0,3]) queue can be set as validate?
Except that, the patch is Reviewed-by: Prike Liang <Prike.Liang@xxxxxxx>.
>
> for (i = 0; i < AMDGPU_MES_MAX_SDMA_PIPES; i++) {
> --
> 2.48.1
